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feat(vmm): MPS support when ACPI is not supported/available #1840

@rinor

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@rinor

Well probably on Firecracker it works (kind of) because afaik Firecracker does not implement/support ACPI, which is used by nanos for power handling and CPU(s) discovery.

Hence nanos, from what I understand, being unable to process MP detection without ACPI support, (couldn't find anything related to MP Floating Pointer Structure/MP Configuration Table parsing), falls back to single CPU by default (no matter the VM config you provide to it)

Firecracker nanos

we pass 4 vcpus, but still nanos starts just 1

  "machine-config": {
    "vcpu_count": 4,
    "cpu_template": "None",
    "smt": false,
    "mem_size_mib": 2000,
    "track_dirty_pages": true
  }

nanos output:

INIT: init_service
INIT: physical memory:
INIT:  [0000000000400000, 000000007ceff000)
INIT: parsing cmdline
INIT: in init_service_new_stack
INIT: init_hwrand
INIT: init cpu features
INIT: calling kernel_runtime_init
ACPI: find_rsdp: could not find valid RSDP
ACPI: AcpiInitializeTables returned 5
APIC: walking MADT table...
APIC: MADT not found, detecting apic interface...
x2APIC: x2APIC detected
APIC: using x2APIC interface
x2APIC: per cpu init, writing 0xc00
x2APIC: read from reg 0x803
x2APIC:  -> read 0x50014
x2APIC: read from reg 0x802
x2APIC:  -> read 0x0
x2APIC: apic id 0, apic ver 50014
x2APIC: write to reg 0x80f, val 0x120
x2APIC: write to reg 0x835, val 0x10000
x2APIC: write to reg 0x836, val 0x10000
x2APIC: write to reg 0x837, val 0x21
x2APIC: write to reg 0x832, val 0x40024
INIT: KVM detected
warning: ACPI MADT not found, default to 1 processor
INIT: init_mxcsr
INIT: starting APs
INIT: started 1 total processors
INIT: hypervisor undetected or HVM platform; registering all PCI drivers...
x2APIC: read from reg 0x802
x2APIC:  -> read 0x0
x2APIC: read from reg 0x802
x2APIC:  -> read 0x0
ACPI: AcpiEnableSubsystem returned 2
x2APIC: write to reg 0x80b, val 0x0
x2APIC: write to reg 0x80b, val 0x0
x2APIC: write to reg 0x80b, val 0x0
x2APIC: write to reg 0x80b, val 0x0
x2APIC: write to reg 0x80b, val 0x0
x2APIC: write to reg 0x80b, val 0x0

Originally posted by @rinor in #1838 (comment)

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