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arsenmarsenm
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AMDGPU: Materialize bitwise not of inline immediates (#95960)
If we have a bitwise negated inline immediate, we can materialize it with s_not_b32/v_not_b32. This mirrors the current bitreverse handling. As a side effect, we also now handle the bitreversed FP immediate case. One test shows some VOPD regressions on gfx11 which should probably be fixed. Previously the 2 v_mov_b32 could be packed, but now the mismatched opcode + mov can't. This problem already already existed for the bfrev case, it just happens more often now.
1 parent 9b78ddf commit 73a2232

16 files changed

+310
-92
lines changed

‎llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp‎

Lines changed: 41 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,6 @@ class SIShrinkInstructions : public MachineFunctionPass {
4545
bool isKImmOperand(const MachineOperand &Src) const;
4646
bool isKUImmOperand(const MachineOperand &Src) const;
4747
bool isKImmOrKUImmOperand(const MachineOperand &Src, bool &IsUnsigned) const;
48-
bool isReverseInlineImm(const MachineOperand &Src, int32_t &ReverseImm) const;
4948
void copyExtraImplicitOps(MachineInstr &NewMI, MachineInstr &MI) const;
5049
void shrinkScalarCompare(MachineInstr &MI) const;
5150
void shrinkMIMG(MachineInstr &MI) const;
@@ -183,15 +182,36 @@ bool SIShrinkInstructions::isKImmOrKUImmOperand(const MachineOperand &Src,
183182
return false;
184183
}
185184

186-
/// \returns true if the constant in \p Src should be replaced with a bitreverse
187-
/// of an inline immediate.
188-
bool SIShrinkInstructions::isReverseInlineImm(const MachineOperand &Src,
189-
int32_t &ReverseImm) const {
190-
if (!isInt<32>(Src.getImm()) || TII->isInlineConstant(Src))
191-
return false;
185+
/// \returns the opcode of an instruction a move immediate of the constant \p
186+
/// Src can be replaced with if the constant is replaced with \p ModifiedImm.
187+
/// i.e.
188+
///
189+
/// If the bitreverse of a constant is an inline immediate, reverse the
190+
/// immediate and return the bitreverse opcode.
191+
///
192+
/// If the bitwise negation of a constant is an inline immediate, reverse the
193+
/// immediate and return the bitwise not opcode.
194+
static unsigned canModifyToInlineImmOp32(const SIInstrInfo *TII,
195+
const MachineOperand &Src,
196+
int32_t &ModifiedImm, bool Scalar) {
197+
if (TII->isInlineConstant(Src))
198+
return 0;
199+
int32_t SrcImm = static_cast<int32_t>(Src.getImm());
200+
201+
if (!Scalar) {
202+
// We could handle the scalar case with here, but we would need to check
203+
// that SCC is not live as S_NOT_B32 clobbers it. It's probably not worth
204+
// it, as the reasonable values are already covered by s_movk_i32.
205+
ModifiedImm = ~SrcImm;
206+
if (TII->isInlineConstant(APInt(32, ModifiedImm)))
207+
return AMDGPU::V_NOT_B32_e32;
208+
}
209+
210+
ModifiedImm = reverseBits<int32_t>(SrcImm);
211+
if (TII->isInlineConstant(APInt(32, ModifiedImm)))
212+
return Scalar ? AMDGPU::S_BREV_B32 : AMDGPU::V_BFREV_B32_e32;
192213

193-
ReverseImm = reverseBits<int32_t>(static_cast<int32_t>(Src.getImm()));
194-
return ReverseImm >= -16 && ReverseImm <= 64;
214+
return 0;
195215
}
196216

197217
/// Copy implicit register operands from specified instruction to this
@@ -801,10 +821,12 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
801821
// XXX - not exactly a check for post-regalloc run.
802822
MachineOperand &Src = MI.getOperand(1);
803823
if (Src.isImm() && MI.getOperand(0).getReg().isPhysical()) {
804-
int32_t ReverseImm;
805-
if (isReverseInlineImm(Src, ReverseImm)) {
806-
MI.setDesc(TII->get(AMDGPU::V_BFREV_B32_e32));
807-
Src.setImm(ReverseImm);
824+
int32_t ModImm;
825+
unsigned ModOpcode =
826+
canModifyToInlineImmOp32(TII, Src, ModImm, /*Scalar=*/false);
827+
if (ModOpcode != 0) {
828+
MI.setDesc(TII->get(ModOpcode));
829+
Src.setImm(static_cast<int64_t>(ModImm));
808830
continue;
809831
}
810832
}
@@ -863,13 +885,15 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
863885
MachineOperand &Src = MI.getOperand(1);
864886

865887
if (Src.isImm() && Dst.getReg().isPhysical()) {
866-
int32_t ReverseImm;
888+
unsigned ModOpc;
889+
int32_t ModImm;
867890
if (isKImmOperand(Src)) {
868891
MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));
869892
Src.setImm(SignExtend64(Src.getImm(), 32));
870-
} else if (isReverseInlineImm(Src, ReverseImm)) {
871-
MI.setDesc(TII->get(AMDGPU::S_BREV_B32));
872-
Src.setImm(ReverseImm);
893+
} else if ((ModOpc = canModifyToInlineImmOp32(TII, Src, ModImm,
894+
/*Scalar=*/true))) {
895+
MI.setDesc(TII->get(ModOpc));
896+
Src.setImm(static_cast<int64_t>(ModImm));
873897
}
874898
}
875899

‎llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -178,7 +178,7 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
178178
; GFX8-LABEL: v_add_v2i16_neg_inline_imm_splat:
179179
; GFX8: ; %bb.0:
180180
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
181-
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffc0
181+
; GFX8-NEXT: v_not_b32_e32 v1, 63
182182
; GFX8-NEXT: v_add_u16_e32 v2, 0xffc0, v0
183183
; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
184184
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
@@ -244,7 +244,7 @@ define <2 x i16> @v_add_v2i16_neg_inline_imm_hi(<2 x i16> %a) {
244244
; GFX8-LABEL: v_add_v2i16_neg_inline_imm_hi:
245245
; GFX8: ; %bb.0:
246246
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
247-
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffc0
247+
; GFX8-NEXT: v_not_b32_e32 v1, 63
248248
; GFX8-NEXT: v_add_u16_e32 v2, 4, v0
249249
; GFX8-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
250250
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1486,7 +1486,7 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
14861486
; GFX6: ; %bb.0:
14871487
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
14881488
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
1489-
; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
1489+
; GFX6-NEXT: v_not_b32_e32 v1, 23
14901490
; GFX6-NEXT: s_and_b32 s2, s2, 0xffffff
14911491
; GFX6-NEXT: s_bfe_u32 s1, s1, 0x170001
14921492
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
@@ -1516,7 +1516,7 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
15161516
; GFX8: ; %bb.0:
15171517
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
15181518
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
1519-
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
1519+
; GFX8-NEXT: v_not_b32_e32 v1, 23
15201520
; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff
15211521
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x170001
15221522
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
@@ -1546,7 +1546,7 @@ define amdgpu_ps i24 @s_fshl_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
15461546
; GFX9: ; %bb.0:
15471547
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
15481548
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
1549-
; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
1549+
; GFX9-NEXT: v_not_b32_e32 v1, 23
15501550
; GFX9-NEXT: s_and_b32 s2, s2, 0xffffff
15511551
; GFX9-NEXT: s_bfe_u32 s1, s1, 0x170001
15521552
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
@@ -1646,7 +1646,7 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
16461646
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16471647
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
16481648
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
1649-
; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffffe8
1649+
; GFX6-NEXT: v_not_b32_e32 v4, 23
16501650
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
16511651
; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 23
16521652
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
@@ -1676,7 +1676,7 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
16761676
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16771677
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
16781678
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
1679-
; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffffe8
1679+
; GFX8-NEXT: v_not_b32_e32 v4, 23
16801680
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
16811681
; GFX8-NEXT: v_bfe_u32 v1, v1, 1, 23
16821682
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
@@ -1706,7 +1706,7 @@ define i24 @v_fshl_i24(i24 %lhs, i24 %rhs, i24 %amt) {
17061706
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
17071707
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
17081708
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
1709-
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffffe8
1709+
; GFX9-NEXT: v_not_b32_e32 v4, 23
17101710
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
17111711
; GFX9-NEXT: v_bfe_u32 v1, v1, 1, 23
17121712
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
@@ -1822,7 +1822,7 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
18221822
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
18231823
; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
18241824
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
1825-
; GFX6-NEXT: v_mov_b32_e32 v3, 0xffffffe8
1825+
; GFX6-NEXT: v_not_b32_e32 v3, 23
18261826
; GFX6-NEXT: s_or_b32 s6, s8, s6
18271827
; GFX6-NEXT: v_or_b32_e32 v0, s0, v0
18281828
; GFX6-NEXT: s_lshr_b32 s0, s2, 16
@@ -1959,7 +1959,7 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
19591959
; GFX8-NEXT: s_or_b32 s2, s2, s6
19601960
; GFX8-NEXT: s_lshl_b32 s3, s3, 8
19611961
; GFX8-NEXT: s_and_b32 s6, s9, 0xff
1962-
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
1962+
; GFX8-NEXT: v_not_b32_e32 v1, 23
19631963
; GFX8-NEXT: s_or_b32 s3, s8, s3
19641964
; GFX8-NEXT: s_and_b32 s6, 0xffff, s6
19651965
; GFX8-NEXT: v_mul_lo_u32 v1, v0, v1
@@ -2079,7 +2079,7 @@ define amdgpu_ps i48 @s_fshl_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
20792079
; GFX9-NEXT: s_or_b32 s2, s2, s6
20802080
; GFX9-NEXT: s_lshl_b32 s3, s3, 8
20812081
; GFX9-NEXT: s_and_b32 s6, s9, 0xff
2082-
; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
2082+
; GFX9-NEXT: v_not_b32_e32 v1, 23
20832083
; GFX9-NEXT: s_or_b32 s3, s8, s3
20842084
; GFX9-NEXT: s_and_b32 s6, 0xffff, s6
20852085
; GFX9-NEXT: v_mul_lo_u32 v1, v0, v1
@@ -2414,7 +2414,7 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
24142414
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
24152415
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
24162416
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
2417-
; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8
2417+
; GFX6-NEXT: v_not_b32_e32 v7, 23
24182418
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
24192419
; GFX6-NEXT: v_and_b32_e32 v5, 0xffffff, v5
24202420
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
@@ -2461,7 +2461,7 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
24612461
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
24622462
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
24632463
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
2464-
; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8
2464+
; GFX8-NEXT: v_not_b32_e32 v7, 23
24652465
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
24662466
; GFX8-NEXT: v_and_b32_e32 v5, 0xffffff, v5
24672467
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
@@ -2508,7 +2508,7 @@ define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
25082508
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
25092509
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
25102510
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
2511-
; GFX9-NEXT: v_mov_b32_e32 v7, 0xffffffe8
2511+
; GFX9-NEXT: v_not_b32_e32 v7, 23
25122512
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
25132513
; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v5
25142514
; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1487,7 +1487,7 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
14871487
; GFX6: ; %bb.0:
14881488
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
14891489
; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
1490-
; GFX6-NEXT: v_mov_b32_e32 v1, 0xffffffe8
1490+
; GFX6-NEXT: v_not_b32_e32 v1, 23
14911491
; GFX6-NEXT: s_and_b32 s2, s2, 0xffffff
14921492
; GFX6-NEXT: s_lshl_b32 s0, s0, 1
14931493
; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
@@ -1518,7 +1518,7 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
15181518
; GFX8: ; %bb.0:
15191519
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
15201520
; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
1521-
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
1521+
; GFX8-NEXT: v_not_b32_e32 v1, 23
15221522
; GFX8-NEXT: s_and_b32 s2, s2, 0xffffff
15231523
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
15241524
; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
@@ -1549,7 +1549,7 @@ define amdgpu_ps i24 @s_fshr_i24(i24 inreg %lhs, i24 inreg %rhs, i24 inreg %amt)
15491549
; GFX9: ; %bb.0:
15501550
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, 24
15511551
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
1552-
; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
1552+
; GFX9-NEXT: v_not_b32_e32 v1, 23
15531553
; GFX9-NEXT: s_and_b32 s2, s2, 0xffffff
15541554
; GFX9-NEXT: s_and_b32 s1, s1, 0xffffff
15551555
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
@@ -1652,7 +1652,7 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
16521652
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16531653
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
16541654
; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
1655-
; GFX6-NEXT: v_mov_b32_e32 v4, 0xffffffe8
1655+
; GFX6-NEXT: v_not_b32_e32 v4, 23
16561656
; GFX6-NEXT: v_and_b32_e32 v2, 0xffffff, v2
16571657
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 1, v0
16581658
; GFX6-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
@@ -1683,7 +1683,7 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
16831683
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
16841684
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
16851685
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
1686-
; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffffe8
1686+
; GFX8-NEXT: v_not_b32_e32 v4, 23
16871687
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
16881688
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
16891689
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
@@ -1714,7 +1714,7 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
17141714
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
17151715
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v3, 24
17161716
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v3
1717-
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffffffe8
1717+
; GFX9-NEXT: v_not_b32_e32 v4, 23
17181718
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v2
17191719
; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff, v1
17201720
; GFX9-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
@@ -1820,7 +1820,7 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
18201820
; GFX6-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
18211821
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
18221822
; GFX6-NEXT: v_mov_b32_e32 v0, s0
1823-
; GFX6-NEXT: v_mov_b32_e32 v3, 0xffffffe8
1823+
; GFX6-NEXT: v_not_b32_e32 v3, 23
18241824
; GFX6-NEXT: s_lshr_b32 s6, s0, 16
18251825
; GFX6-NEXT: s_and_b32 s8, s0, 0xff
18261826
; GFX6-NEXT: s_lshl_b32 s9, s9, 8
@@ -1962,7 +1962,7 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
19621962
; GFX8-NEXT: s_or_b32 s2, s2, s8
19631963
; GFX8-NEXT: s_lshl_b32 s3, s3, 8
19641964
; GFX8-NEXT: s_and_b32 s8, s11, 0xff
1965-
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffe8
1965+
; GFX8-NEXT: v_not_b32_e32 v1, 23
19661966
; GFX8-NEXT: s_or_b32 s3, s10, s3
19671967
; GFX8-NEXT: s_and_b32 s8, 0xffff, s8
19681968
; GFX8-NEXT: v_mul_lo_u32 v1, v0, v1
@@ -2082,7 +2082,7 @@ define amdgpu_ps i48 @s_fshr_v2i24(i48 inreg %lhs.arg, i48 inreg %rhs.arg, i48 i
20822082
; GFX9-NEXT: s_or_b32 s2, s2, s8
20832083
; GFX9-NEXT: s_lshl_b32 s3, s3, 8
20842084
; GFX9-NEXT: s_and_b32 s8, s11, 0xff
2085-
; GFX9-NEXT: v_mov_b32_e32 v1, 0xffffffe8
2085+
; GFX9-NEXT: v_not_b32_e32 v1, 23
20862086
; GFX9-NEXT: s_or_b32 s3, s10, s3
20872087
; GFX9-NEXT: s_and_b32 s8, 0xffff, s8
20882088
; GFX9-NEXT: v_mul_lo_u32 v1, v0, v1
@@ -2424,7 +2424,7 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
24242424
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
24252425
; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
24262426
; GFX6-NEXT: v_rcp_iflag_f32_e32 v6, v6
2427-
; GFX6-NEXT: v_mov_b32_e32 v7, 0xffffffe8
2427+
; GFX6-NEXT: v_not_b32_e32 v7, 23
24282428
; GFX6-NEXT: v_and_b32_e32 v4, 0xffffff, v4
24292429
; GFX6-NEXT: v_and_b32_e32 v5, 0xffffff, v5
24302430
; GFX6-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
@@ -2473,7 +2473,7 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
24732473
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
24742474
; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
24752475
; GFX8-NEXT: v_rcp_iflag_f32_e32 v6, v6
2476-
; GFX8-NEXT: v_mov_b32_e32 v7, 0xffffffe8
2476+
; GFX8-NEXT: v_not_b32_e32 v7, 23
24772477
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
24782478
; GFX8-NEXT: v_and_b32_e32 v5, 0xffffff, v5
24792479
; GFX8-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
@@ -2522,7 +2522,7 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
25222522
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
25232523
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v6, 24
25242524
; GFX9-NEXT: v_rcp_iflag_f32_e32 v6, v6
2525-
; GFX9-NEXT: v_mov_b32_e32 v7, 0xffffffe8
2525+
; GFX9-NEXT: v_not_b32_e32 v7, 23
25262526
; GFX9-NEXT: v_and_b32_e32 v4, 0xffffff, v4
25272527
; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v5
25282528
; GFX9-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -865,7 +865,7 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
865865
; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
866866
; GFX1030-NEXT: flat_load_dword v2, v[0:1]
867867
; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c7
868-
; GFX1030-NEXT: v_mov_b32_e32 v1, 0x102
868+
; GFX1030-NEXT: v_bfrev_b32_e32 v1, 4.0
869869
; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
870870
; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[0:3]
871871
; GFX1030-NEXT: s_waitcnt vmcnt(0)
@@ -894,7 +894,7 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
894894
; GFX1013-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
895895
; GFX1013-NEXT: flat_load_dword v2, v[0:1]
896896
; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c7
897-
; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102
897+
; GFX1013-NEXT: v_bfrev_b32_e32 v1, 4.0
898898
; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
899899
; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:11], s[4:7]
900900
; GFX1013-NEXT: s_waitcnt vmcnt(0)
@@ -973,7 +973,7 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
973973
; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
974974
; GFX1030-NEXT: flat_load_dword v2, v[0:1]
975975
; GFX1030-NEXT: v_mov_b32_e32 v0, 0xb36211c6
976-
; GFX1030-NEXT: v_mov_b32_e32 v1, 0x102
976+
; GFX1030-NEXT: v_bfrev_b32_e32 v1, 4.0
977977
; GFX1030-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
978978
; GFX1030-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[0:3] a16
979979
; GFX1030-NEXT: s_waitcnt vmcnt(0)
@@ -999,7 +999,7 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
999999
; GFX1013-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
10001000
; GFX1013-NEXT: flat_load_dword v2, v[0:1]
10011001
; GFX1013-NEXT: v_mov_b32_e32 v0, 0xb36211c6
1002-
; GFX1013-NEXT: v_mov_b32_e32 v1, 0x102
1002+
; GFX1013-NEXT: v_bfrev_b32_e32 v1, 4.0
10031003
; GFX1013-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
10041004
; GFX1013-NEXT: image_bvh64_intersect_ray v[0:3], v[0:8], s[4:7] a16
10051005
; GFX1013-NEXT: s_waitcnt vmcnt(0)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ define <2 x i16> @v_sub_v2i16_neg_inline_imm_splat(<2 x i16> %a) {
147147
; GFX8-LABEL: v_sub_v2i16_neg_inline_imm_splat:
148148
; GFX8: ; %bb.0:
149149
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
150-
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffc0
150+
; GFX8-NEXT: v_not_b32_e32 v1, 63
151151
; GFX8-NEXT: v_subrev_u16_e32 v2, 0xffc0, v0
152152
; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
153153
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
@@ -211,7 +211,7 @@ define <2 x i16> @v_sub_v2i16_neg_inline_imm_hi(<2 x i16> %a) {
211211
; GFX8-LABEL: v_sub_v2i16_neg_inline_imm_hi:
212212
; GFX8: ; %bb.0:
213213
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
214-
; GFX8-NEXT: v_mov_b32_e32 v1, 0xffffffc0
214+
; GFX8-NEXT: v_not_b32_e32 v1, 63
215215
; GFX8-NEXT: v_subrev_u16_e32 v2, 4, v0
216216
; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
217217
; GFX8-NEXT: v_or_b32_e32 v0, v2, v0

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