Fix invalid horizontal stride 0 for destination in predicated sub-DW operations

Fixed invalid horizontal stride 0 for destination operand in emitLSCVectorLoad_subDW() function. When doUniformLoad is true, the code was setting hStride to 0 for destination operand, which violates Intel GPU architecture constraints and causes instruction validation errors for i8/i16 predicated load/store operations. Modified the logic to use default stride for uniform loads and appropriate stride (2 or 4) for non-uniform loads, eliminating the invalid stride 0 case.

Author: ustachow

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -17717,8 +17717,10 @@ void EmitPass::emitLSCVectorLoad_subDW(LSC_CACHE_OPTS CacheOpts, bool UseA32, Re
   // Copy merge value to gatherDst now, to avoid predicated copy to original
   // destination later
   if (mergeVal) {
-    uint32_t hStride = doUniformLoad ? 0 : ((EltBytes == 1) ? 4 : 2);
-    m_encoder->SetDstRegion(hStride);
+    if (!doUniformLoad) {
+      uint32_t hStride = (EltBytes == 1) ? 4 : 2;
+      m_encoder->SetDstRegion(hStride);
+    }
     m_encoder->Copy(gatherDstAlias, mergeVal);
     m_encoder->Push();
   }

IGC/Compiler/tests/EmitVISAPass/predicated-load-subdw.ll

@@ -23,7 +23,7 @@ entry:
   ; CHECK: .decl [[G_ALIAS1:.*]] v_type=G type=b num_elts=4 align=wordx32 alias=<[[GATHER1:.*]], 0>
 
   ; copy merge value. do predicated load, copy result
-  ; CHECK: mov (M1_NM, 1) [[G_ALIAS0]](0,0)<0> 0x0:b
+  ; CHECK: mov (M1_NM, 1) [[G_ALIAS0]](0,0)<1> 0x0:b
   ; CHECK: (P1) lsc_load.ugm (M1_NM, 1)  [[GATHER0]]:d8u32  flat[
   ; CHECK: mov (M1_NM, 1) res0(0,0)<1> [[G_ALIAS0]](0,0)<0;1,0>
   %res0 = call i8 @llvm.genx.GenISA.PredicatedLoad.i8.p1.i8(ptr addrspace(1) %in, i64 1, i1 %p, i8 0)