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IGCVectorizer supports PHI for SIMD32
IGCVectorizer supports PHI, insert/extract element instructions for simd32. Other instructions are blacklisted at the moment.
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8 files changed

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-32
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8 files changed

+335
-32
lines changed

‎IGC/Compiler/CISACodeGen/EmitVISAPass.cpp‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -4298,8 +4298,8 @@ void EmitPass::Sub(const SSource sources[2], const DstModifier &modifier) {
42984298

42994299
if (IGC_IS_FLAG_ENABLED(EnableVectorEmitter) && IsPossible) {
43004300

4301-
IGC_ASSERT_EXIT_MESSAGE(m_encoder->GetSimdSize() == lanesToSIMDMode(16),
4302-
"As of now Vector Emission is only supported for SIMD16");
4301+
IGC_ASSERT_MESSAGE(m_encoder->GetSimdSize() == lanesToSIMDMode(16),
4302+
"As of now Vector Emission is only supported for SIMD16");
43034303

43044304
unsigned VectorSize = getVectorSize(sources[0].value);
43054305
IGC_ASSERT_MESSAGE(VectorSize == getVectorSize(sources[1].value), "operands must have same vector types");
@@ -4389,8 +4389,8 @@ void EmitPass::Add(const SSource sources[2], const DstModifier &modifier) {
43894389

43904390
if (IGC_IS_FLAG_ENABLED(EnableVectorEmitter) && IsPossible) {
43914391

4392-
IGC_ASSERT_EXIT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4393-
"As of now Vector Emission is only supported for SIMD16");
4392+
IGC_ASSERT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4393+
"As of now Vector Emission is only supported for SIMD16");
43944394

43954395
bool AllUniform = src[0]->IsUniform() && src[1]->IsUniform() && m_destination->IsUniform();
43964396
// cannot emit 16 SIMD if SIMD SIZE is set to 8, but can emit 4
@@ -4448,8 +4448,8 @@ void EmitPass::Mul(const SSource sources[2], const DstModifier &modifier) {
44484448

44494449
if (IGC_IS_FLAG_ENABLED(EnableVectorEmitter) && IsPossible) {
44504450

4451-
IGC_ASSERT_EXIT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4452-
"As of now Vector Emission is only supported for SIMD16");
4451+
IGC_ASSERT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4452+
"As of now Vector Emission is only supported for SIMD16");
44534453
unsigned VectorSize = getVectorSize(sources[0].value);
44544454
IGC_ASSERT_MESSAGE(VectorSize == getVectorSize(sources[1].value), "operands must have same vector types");
44554455

@@ -4528,8 +4528,8 @@ void EmitPass::Div(const SSource sources[2], const DstModifier &modifier) {
45284528
if (IGC_IS_FLAG_ENABLED(EnableVectorEmitter) && sources[0].value->getType()->isVectorTy() &&
45294529
sources[1].value->getType()->isVectorTy()) {
45304530

4531-
IGC_ASSERT_EXIT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4532-
"As of now Vector Emission is only supported for SIMD16");
4531+
IGC_ASSERT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4532+
"As of now Vector Emission is only supported for SIMD16");
45334533
unsigned VectorSize = getVectorSize(sources[0].value);
45344534

45354535
for (unsigned i = 0; i < VectorSize; ++i) {
@@ -4561,8 +4561,8 @@ void EmitPass::Inv(const SSource sources[2], const DstModifier &modifier) {
45614561
if (IGC_IS_FLAG_ENABLED(EnableVectorEmitter) && sources[0].value->getType()->isVectorTy() &&
45624562
sources[1].value->getType()->isVectorTy()) {
45634563

4564-
IGC_ASSERT_EXIT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4565-
"As of now Vector Emission is only supported for SIMD16");
4564+
IGC_ASSERT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4565+
"As of now Vector Emission is only supported for SIMD16");
45664566
unsigned VectorSize = getVectorSize(sources[0].value);
45674567

45684568
CVariable *src[1];
@@ -4596,8 +4596,8 @@ void EmitPass::MaxNum(const SSource sources[2], const DstModifier &modifier) {
45964596
if (IGC_IS_FLAG_ENABLED(EnableVectorEmitter) && sources[0].value->getType()->isVectorTy() &&
45974597
sources[1].value->getType()->isVectorTy()) {
45984598

4599-
IGC_ASSERT_EXIT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4600-
"As of now Vector Emission is only supported for SIMD16");
4599+
IGC_ASSERT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4600+
"As of now Vector Emission is only supported for SIMD16");
46014601
unsigned VectorSize = getVectorSize(sources[0].value);
46024602

46034603
bool AllUniform = src[0]->IsUniform() && src[1]->IsUniform() && m_destination->IsUniform();
@@ -4640,16 +4640,16 @@ void EmitPass::MaxNum(const SSource sources[2], const DstModifier &modifier) {
46404640
return;
46414641
}
46424642

4643-
IGC_ASSERT_EXIT_MESSAGE(0, " if we are at this part, something went wrong "
4644-
"with maxnum vectorization");
4643+
IGC_ASSERT_MESSAGE(0, " if we are at this part, something went wrong "
4644+
"with maxnum vectorization");
46454645
}
46464646

46474647
void EmitPass::Exp2(const SSource sources[2], const DstModifier &modifier) {
46484648

46494649
if (IGC_IS_FLAG_ENABLED(EnableVectorEmitter) && sources[0].value->getType()->isVectorTy()) {
46504650

4651-
IGC_ASSERT_EXIT_MESSAGE(m_encoder->GetSimdSize() == lanesToSIMDMode(16),
4652-
"As of now Vector Emission is only supported for SIMD16");
4651+
IGC_ASSERT_MESSAGE(m_encoder->GetSimdSize() == lanesToSIMDMode(16),
4652+
"As of now Vector Emission is only supported for SIMD16");
46534653

46544654
unsigned VectorSize = getVectorSize(sources[0].value);
46554655

@@ -4747,8 +4747,8 @@ void EmitPass::FDiv(const SSource sources[2], const DstModifier &modifier) {
47474747

47484748
if (IGC_IS_FLAG_ENABLED(EnableVectorEmitter) && IsPossible) {
47494749

4750-
IGC_ASSERT_EXIT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4751-
"As of now Vector Emission is only supported for SIMD16");
4750+
IGC_ASSERT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4751+
"As of now Vector Emission is only supported for SIMD16");
47524752
if (isVectorOfOnes(sources[0].value))
47534753
Inv(sources, modifier);
47544754
else
@@ -4807,8 +4807,8 @@ void EmitPass::VectorCMP(llvm::CmpInst::Predicate pred, const SSource sources[2]
48074807
dst = m_currShader->BitCast(m_destination, src[0]->GetType());
48084808
}
48094809

4810-
IGC_ASSERT_EXIT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4811-
"As of now Vector Emission is only supported for SIMD16");
4810+
IGC_ASSERT_MESSAGE(numLanes(m_encoder->GetSimdSize()) == 16,
4811+
"As of now Vector Emission is only supported for SIMD16");
48124812
unsigned VectorSize = getVectorSize(sources[0].value);
48134813

48144814
bool AllUniform = src[0]->IsUniform() && src[1]->IsUniform() && m_destination->IsUniform();
@@ -4818,7 +4818,6 @@ void EmitPass::VectorCMP(llvm::CmpInst::Predicate pred, const SSource sources[2]
48184818
bool CanEmitThisSize = VectorSize <= SIMDSize;
48194819

48204820
if (IGC_IS_FLAG_ENABLED(VectorizerUniformValueVectorizationEnabled) && AllUniform && CanEmitThisSize) {
4821-
48224821
m_encoder->SetSrcRegion(0, 1, 1, 0);
48234822
m_encoder->SetSrcRegion(1, 1, 1, 0);
48244823
m_encoder->SetUniformSIMDSize(lanesToSIMDMode(VectorSize));
@@ -5025,6 +5024,7 @@ void EmitPass::VectorSelect(const SSource sources[3], const DstModifier &modifie
50255024
}
50265025

50275026
bool PredicateLengthIsCorrect = flag->GetNumberElement() == 1 || flag->GetNumberElement() == SIMDSize;
5027+
50285028
IGC_ASSERT_EXIT_MESSAGE(PredicateLengthIsCorrect, "we can only emit non-uniform selects with matching predicate");
50295029

50305030
for (unsigned i = 0; i < VectorSize; ++i) {

‎IGC/Compiler/CISACodeGen/IGCVectorizer.cpp‎

Lines changed: 27 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -295,7 +295,14 @@ bool isAllowedStub(Instruction *I) {
295295
return Result;
296296
}
297297

298-
bool isSafeToVectorize(Instruction *I) {
298+
bool IGCVectorizer::isSafeToVectorizeSIMD32(Instruction *I) {
299+
bool IsExtract = llvm::isa<ExtractElementInst>(I);
300+
bool IsInsert = llvm::isa<InsertElementInst>(I);
301+
bool Result = isPHISafe(I) || IsExtract || IsInsert;
302+
return Result;
303+
}
304+
305+
bool IGCVectorizer::isSafeToVectorizeSIMD16(Instruction *I) {
299306

300307
bool IsExtract = llvm::isa<ExtractElementInst>(I);
301308
bool IsInsert = llvm::isa<InsertElementInst>(I);
@@ -323,6 +330,17 @@ bool isSafeToVectorize(Instruction *I) {
323330
return Result;
324331
}
325332

333+
bool IGCVectorizer::isSafeToVectorize(Instruction *I) {
334+
335+
if (SIMDSize == 16)
336+
return isSafeToVectorizeSIMD16(I);
337+
else if (SIMDSize == 32)
338+
return isSafeToVectorizeSIMD32(I);
339+
else
340+
IGC_ASSERT_EXIT_MESSAGE(0, "not supported simd");
341+
return false;
342+
}
343+
326344
bool IGCVectorizer::handleStub(VecArr &Slice) {
327345
PRINT_LOG("stub vectorization: ");
328346
PRINT_INST_NL(Slice.front());
@@ -1400,31 +1418,31 @@ void IGCVectorizer::collectInstructionToProcess(VecArr &ToProcess, Function &F)
14001418
}
14011419
}
14021420

1403-
bool IGCVectorizer::checkIfSIMD16(llvm::Function &F) {
1421+
unsigned IGCVectorizer::checkSIMD(llvm::Function &F) {
14041422

14051423
MDUtils = getAnalysis<MetaDataUtilsWrapper>().getMetaDataUtils();
1406-
bool Result = false;
1424+
unsigned SimdSize = 0;
14071425
if (MDUtils->findFunctionsInfoItem(&F) != MDUtils->end_FunctionsInfo()) {
14081426
IGC::IGCMD::FunctionInfoMetaDataHandle funcInfoMD = MDUtils->getFunctionsInfoItem(&F);
1409-
unsigned SimdSize = funcInfoMD->getSubGroupSize()->getSIMDSize();
1410-
Result = SimdSize == 16;
1427+
SimdSize = funcInfoMD->getSubGroupSize()->getSIMDSize();
14111428
}
14121429

1413-
return Result;
1430+
return SimdSize;
14141431
}
14151432

14161433
bool IGCVectorizer::runOnFunction(llvm::Function &F) {
14171434

1418-
// DPAS only allowed in simd16 mode + helps to reduce untested cases
1419-
if (!checkIfSIMD16(F))
1435+
SIMDSize = checkSIMD(F);
1436+
if (SIMDSize == 0)
14201437
return false;
14211438

14221439
WI = &getAnalysis<WIAnalysis>();
14231440

14241441
M = F.getParent();
14251442
CGCtx = getAnalysis<CodeGenContextWrapper>().getCodeGenContext();
14261443
initializeLogFile(F);
1427-
PRINT_LOG_NL("vectorizer: fadd, fdiv, fptrunc");
1444+
PRINT_LOG_NL(" SIMD Size: " << SIMDSize);
1445+
PRINT_LOG_NL("vectorizer: fadd, fdiv, fptrunc, select, cmp, intrinsics, genintrinsics, simd32");
14281446

14291447
VecArr ToProcess;
14301448
// we collect operands that seem promising for vectorization

‎IGC/Compiler/CISACodeGen/IGCVectorizer.h‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -71,10 +71,15 @@ class IGCVectorizer : public llvm::FunctionPass {
7171
std::string LogStr;
7272
llvm::raw_string_ostream OutputLogStream = raw_string_ostream(LogStr);
7373
Module *M = nullptr;
74-
bool checkIfSIMD16(llvm::Function &F);
74+
unsigned SIMDSize = 0;
75+
unsigned checkSIMD(llvm::Function &F);
7576
void initializeLogFile(Function &F);
7677
void writeLog();
7778

79+
bool isSafeToVectorize(llvm::Instruction *I);
80+
bool isSafeToVectorizeSIMD16(llvm::Instruction *I);
81+
bool isSafeToVectorizeSIMD32(llvm::Instruction *I);
82+
7883
void findInsertElementsInDataFlow(llvm::Instruction *I, VecArr &Chain);
7984
bool checkSlice(VecArr &Slice, InsertStruct &InSt);
8085
bool processChain(InsertStruct &InSt);

‎IGC/Compiler/tests/EmitVISAPass/vectorizer-emission-select.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
; SPDX-License-Identifier: MIT
66
;
77
;============================ end_copyright_notice =============================
8-
; REQUIRES: regkeys, llvm-16-plus, debug
8+
; REQUIRES: regkeys, llvm-16-plus
99
; RUN: igc_opt -S %s --opaque-pointers -dce -platformbmg -igc-emit-visa --regkey=DumpVISAASMToConsole=1 -simd-mode 16 &> %t_output.ll
1010
; RUN: FileCheck --input-file %t_output.ll %s
1111

‎IGC/Compiler/tests/EmitVISAPass/vectorizer-emission-simd32-phi-dpas-basic.ll‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,54 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2025 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
9+
; REQUIRES: regkeys, llvm-16-plus
10+
; RUN: igc_opt -S %s -opaque-pointers -platformbmg -igc-emit-visa --regkey=DumpVISAASMToConsole=1 -simd-mode 32 &> %t_output.ll
11+
; RUN: FileCheck --input-file %t_output.ll %s
12+
13+
; CHECK: .decl vectorized_phi v_type=G type=f num_elts=128 align=wordx32
14+
; CHECK: .decl vectorized_phi71 v_type=G type=f num_elts=128 align=wordx32
15+
; CHECK: .kernel_attr SimdSize=32
16+
17+
; CHECK: mov (M1, 32) vectorized_phi(0,0)<1> 0x0:f
18+
; CHECK: mov (M1, 32) vectorized_phi(2,0)<1> 0x0:f
19+
; CHECK: mov (M1, 32) vectorized_phi(4,0)<1> 0x0:f
20+
; CHECK: mov (M1, 32) vectorized_phi(6,0)<1> 0x0:f
21+
; CHECK: mov (M1, 32) vectorized_phi71(0,0)<1> 0x0:f
22+
; CHECK: mov (M1, 32) vectorized_phi71(2,0)<1> 0x0:f
23+
; CHECK: mov (M1, 32) vectorized_phi71(4,0)<1> 0x0:f
24+
; CHECK: mov (M1, 32) vectorized_phi71(6,0)<1> 0x0:f
25+
26+
; CHECK: dpas.bf.bf.8.8 (M1, 16) vectorized_phi.0
27+
; CHECK: dpas.bf.bf.8.8 (M1, 16) vectorized_phi71.0
28+
; CHECK: dpas.bf.bf.8.8 (M1, 16) vectorized_phi.0
29+
; CHECK: dpas.bf.bf.8.8 (M1, 16) vectorized_phi71.0
30+
31+
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-n8:16:32"
32+
target triple = "spir64-unknown-unknown"
33+
34+
define spir_kernel void @foo() {
35+
bb:
36+
br label %bb79
37+
38+
bb79: ; preds = %bb79, %bb
39+
%vectorized_phi = phi <4 x float> [ zeroinitializer, %bb ], [ %i264, %bb79 ]
40+
%vectorized_phi71 = phi <4 x float> [ zeroinitializer, %bb ], [ %i265, %bb79 ]
41+
%i248 = call <4 x float> @llvm.genx.GenISA.sub.group.dpas.v4f32.v4f32.v4i16.v4i32(<4 x float> %vectorized_phi, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer, i32 11, i32 11, i32 8, i32 8, i1 false)
42+
%i249 = call <4 x float> @llvm.genx.GenISA.sub.group.dpas.v4f32.v4f32.v4i16.v4i32(<4 x float> %vectorized_phi71, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer, i32 11, i32 11, i32 8, i32 8, i1 false)
43+
%i264 = call <4 x float> @llvm.genx.GenISA.sub.group.dpas.v4f32.v4f32.v4i16.v4i32(<4 x float> %i248, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer, i32 11, i32 11, i32 8, i32 8, i1 false)
44+
%i265 = call <4 x float> @llvm.genx.GenISA.sub.group.dpas.v4f32.v4f32.v4i16.v4i32(<4 x float> %i249, <4 x i16> zeroinitializer, <4 x i32> zeroinitializer, i32 11, i32 11, i32 8, i32 8, i1 false)
45+
br label %bb79
46+
}
47+
48+
declare <4 x float> @llvm.genx.GenISA.sub.group.dpas.v4f32.v4f32.v4i16.v4i32(<4 x float>, <4 x i16>, <4 x i32>, i32, i32, i32, i32, i1)
49+
50+
!igc.functions = !{!0}
51+
52+
!0 = distinct !{ptr @foo, !1}
53+
!1 = distinct !{!2}
54+
!2 = distinct !{!"function_type", i32 0}

‎IGC/Compiler/tests/EmitVISAPass/vectorizer-vector-emission-fmul-disable-simd32.ll‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
;=========================== begin_copyright_notice ============================
2+
;
3+
; Copyright (C) 2025 Intel Corporation
4+
;
5+
; SPDX-License-Identifier: MIT
6+
;
7+
;============================ end_copyright_notice =============================
8+
9+
; REQUIRES: regkeys, llvm-16-plus
10+
11+
; RUN: not --crash igc_opt -S -opaque-pointers -dce -platformpvc -igc-emit-visa --regkey=EnableAssertEvaluation=1 --regkey=EnableAssertProgramTermination=0 --regkey=EnableLogAssertToStderr=1 --regkey=EnableStandardAssert=1 --regkey=DumpVISAASMToConsole=1 -simd-mode 32 < %s &> %t_output.ll
12+
; RUN: FileCheck --input-file %t_output.ll %s
13+
14+
; CHECK: numLanes(m_encoder->GetSimdSize()) == 16, As of now Vector Emission is only supported for SIMD16
15+
16+
define spir_kernel void @widget() {
17+
entry:
18+
br label %._crit_edge
19+
20+
._crit_edge: ; preds = %._crit_edge.._crit_edge_crit_edge, %6
21+
%vectorized_phi = phi <8 x float> [ zeroinitializer, %entry ], [ %result, %._crit_edge.._crit_edge_crit_edge ]
22+
%vector = insertelement <8 x float> zeroinitializer, float 0.000000e+00, i64 0
23+
%vectorized_binary = fmul <8 x float> %vector, %vectorized_phi
24+
%result = call <8 x float> @llvm.genx.GenISA.sub.group.dpas.v8f32.v8f32.v8i16.v8i32(<8 x float> %vectorized_binary, <8 x i16> zeroinitializer, <8 x i32> zeroinitializer, i32 0, i32 0, i32 0, i32 0, i1 false)
25+
br label %._crit_edge.._crit_edge_crit_edge
26+
27+
._crit_edge.._crit_edge_crit_edge: ; preds = %._crit_edge
28+
br label %._crit_edge
29+
}
30+
31+
declare <8 x float> @llvm.genx.GenISA.sub.group.dpas.v8f32.v8f32.v8i16.v8i32(<8 x float>, <8 x i16>, <8 x i32>, i32, i32, i32, i32, i1)
32+
33+
!igc.functions = !{!0}
34+
35+
!0 = distinct !{ptr @widget, !1}
36+
!1 = distinct !{!2}
37+
!2 = distinct !{!"function_type", i32 0}

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