Fix a recent regression in atomics support

A recent update changed the types of the bit-fields in ATOMIC_INFO from
unsigned int to enum types.  This resulted in the values of those
fields being incorrectly sign extended when extracted from the struct.
Fix the problem by changing the fields of ATOMIC_INFO to not be
bit-fields.  This required changing the code that encodes/decodes
ATOMIC_INFO to/from an int.

Author: gklimowicz

tools/flang2/flang2exe/iliutil.cpp

@@ -49,11 +49,17 @@
  */
 #include "mth.h"
 
-/** Union used to encode ATOMIC_INFO as an int or decode it.  If
-    sizeof(ATOMIC_INFO)>int, then the union trick cannot be used and we'll have
-    to write explicit bit packing code. */
+/** Union used to encode ATOMIC_INFO as an int or decode it.  The union
+    contains a compacted version of ATOMIC_INFO using bitfields.  The bitfields
+    are unsigned rather than the proper enum type so that the values aren't
+    sign extended when extracted. */
 union ATOMIC_ENCODER {
-  ATOMIC_INFO info;
+  struct {
+    unsigned msz : 8;
+    unsigned op : 8;
+    unsigned origin : 2;
+    unsigned scope : 1;
+  } info;
   int encoding;
 };
 
@@ -13637,7 +13643,7 @@ atomic_encode_aux(MSZ msz, SYNC_SCOPE scope, ATOMIC_ORIGIN origin,
                   ATOMIC_RMW_OP op)
 {
   union ATOMIC_ENCODER u;
-  DEBUG_ASSERT(sizeof(ATOMIC_INFO) <= sizeof(int),
+  DEBUG_ASSERT(sizeof(u.info) <= sizeof(int),
                "need to reimplement atomic_encode");
   DEBUG_ASSERT((unsigned)origin <= (unsigned)AORG_MAX_DEF,
                "atomic_encode_ld_st: bad origin");
@@ -13679,9 +13685,14 @@ atomic_encode_rmw(MSZ msz, SYNC_SCOPE scope, ATOMIC_ORIGIN origin,
 ATOMIC_INFO
 atomic_decode(int encoding)
 {
+  ATOMIC_INFO result;
   union ATOMIC_ENCODER u;
   u.encoding = encoding;
-  return u.info;
+  result.msz = (MSZ) u.info.msz;
+  result.op = (ATOMIC_RMW_OP) u.info.op;
+  result.origin = (ATOMIC_ORIGIN) u.info.origin;
+  result.scope = (SYNC_SCOPE) u.info.scope;
+  return result;
 }
 
 /** Get index of ATOMIC_INFO operand for a given ILI instruction. */

tools/shared/atomic_common.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -105,14 +105,12 @@ typedef struct CMPXCHG_MEMORY_ORDER {
   MEMORY_ORDER failure;
 } CMPXCHG_MEMORY_ORDER;
 
-/** Information about an atomic operation.
-    The fields are declared unsigned because pgcc/pgc++ 17.1 sign-extends
-    them if they are declared as enum types. */
+/** Information about an atomic operation. */
 typedef struct ATOMIC_INFO {
-  MSZ msz : 8; ///< size of memory operand
-  ATOMIC_RMW_OP op : 8; ///< AOP_UNDEF except for ATOMICRMWx instructions
-  ATOMIC_ORIGIN origin : 2;
-  SYNC_SCOPE scope : 1;
+  MSZ msz; ///< size of memory operand
+  ATOMIC_RMW_OP op; ///< AOP_UNDEF except for ATOMICRMWx instructions
+  ATOMIC_ORIGIN origin;
+  SYNC_SCOPE scope;
 } ATOMIC_INFO;
 
 /** True if MEMORY_ORDER m performs an acquire operation.