adnan-reply

[xyjiang1216]

After reading the related questions you posted, I have a few brief opinions:

1. Altera and Xilinx have MAC cores. The ports are definitely not matched. You cannot simply compare with Altera's connection method. You need to read the relevant documents of Xilinx MAC core configuration in detail;
2. You need to understand the direct cross-link interface relationship between MAC core and zc-706;
3. Check the manual of zc-706 to learn about the configuration of the PHY chip (model 88E1116R).

The specific analysis of the issues related to the MAC IP matching file:
Lines 84 and 85: the reference clock and port clock interface of MAC core,
Lines 119-130: the interface with phy chip;
Lines 157-162: the register configuration interface of the MAC core;
adnan-reply.zip

[Adnan1986]

Hello
After checking both tutorials, regarding unmatching ports for the corresponding IP in both Altera and Xilinx.
It sounds for your work(at least in sgmii_pcs IP in Altera) you haven't used MDIO Interface which we have in Xilinx IP and you can see in the(Lines 119-130: the interface with PHY chip) and also there is some register that you used in the Altera IP(Lines 157-162: the register configuration interface of the MAC core) which I couldn't figure out, what is alternative in Xilinx, of course, there are some configuration vectors in Xilinx IP for management but base on data In/Out, I couldn't match them with Altera IP.
I do appreciate it if give me some advice. I don't know whether you have tried the OpenTSN2 on the Xilinx board or not, but your help could help me too much.
Another question is, for OpenTSN2 that you have used Altera board with Arria10 FPGA family, Could you please tell me what board have you used?
Sorry to ask too many questions as you know starting with this project at the beginning raises too many questions for me until figure out the first preliminary TSNSwitch to start working.
Many thanks in advance for your help and time.

MAC IP matching.zip

[xyjiang1216]

Hello, after reading the related questions you sent, I would like to briefly talk about my views
First, the SGMII core used in the implementation of OpenTSN2.0 on Altera is determined that the MDIO port in Xilinx IP will not be used, because the PHY chip model is different, and the configuration is also different certainly;
Second, I feel that you have been entangled in the IP core transplantation of Altera and Xilinx platforms. In my opinion, the connection and use of Altera's IP core is just to give you a reference on the use of IP core, not to say that the IP core usage of these two platforms is the same. What you should know now is the working state of Xilinx's IP core, that is, you should fully understand the state and meaning of each interface of the IP core. For example, interface”.status_vector”，what signal is it? How many states does it has?
Third, the IP core's working state. We use the IP core in Altera. Line 157-162 is the register configuration of the IP core, and the configuration interface of phy is directly connected to the chip pin (because the board is customized, the interface of phy chip has been connected to arria) The IP core can work normally only when phy and register are configured successfully. Refer to page 50 of zc-706 manual to see if these PHY interfaces can be adapted to Xilinx IP core interfaces (lines 119-130), and you need to know the meaning of each interface;
Fourth, the problem of data not going out is probably caused by the unsuccessful configuration of PHY chip;
Fifthly, the Altera board we use here is a customized board, which uses the chip 10ax048h2f34 of Arria 10, and the model of PHY chip is vsc8504.

[Adnan1986]

Many thanks for your complete explanation. I will try to fix this part base on your advice.