Use max CPU clock frequency

Author: bugadani

Cargo.lock

@@ -7,7 +7,7 @@ edition = "2018"
 [dependencies]
 panic-never = "0.1.0"
 ufmt = { version = "0.1.0", optional = true }
-
+cfg-if = "1.0"
 
 [features]
 log = ["ufmt"]
@@ -22,6 +22,9 @@ esp32c5 = []
 esp32c6 = []
 esp32h2 = []
 
+# use max CPU frequency
+max-cpu-frequency = []
+
 [profile.release]
 codegen-units = 1
 debug = false

Cargo.toml

@@ -3,6 +3,7 @@ MEMORY {
     IRAM : ORIGIN = 0x40390000, LENGTH = 0x10000
 }
 
+PROVIDE( ets_delay_us = 0x40000050 );
 PROVIDE( esp_rom_spiflash_wait_idle = 0x4000010c );
 PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000110 );
 PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000114 );

ld/esp32c3.x

@@ -10,6 +10,7 @@ MEMORY {
  * These are all weak symbols that could be overwritten in ESP-IDF.
  */
 
+PROVIDE ( ets_delay_us = 0x4000d888 );
 PROVIDE ( ets_efuse_get_spiconfig = 0x4000e4a0 );
 PROVIDE ( s_cdcacm_old_rts = 0x3ffffd34 );
 PROVIDE ( SelectSpiFunction = 0x40015d08 );

ld/esp32s2.x

@@ -3,16 +3,7 @@ MEMORY {
     IRAM : ORIGIN = 0x40380400, LENGTH = 0x10000
 }
 
-/* ROM function interface esp32s3.rom.ld for esp32s3
- *
- *
- * Generated from ./interface-esp32s3.yml md5sum 39c4ce259b11323b9404c192b01b712b
- *
- * Compatible with ROM where ECO version equal or greater to 0.
- *
- * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
- */
-
+PROVIDE( ets_delay_us = 0x40000600 );
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
 
 /***************************************

ld/esp32s3.x

@@ -46,7 +46,6 @@ extern "C" {
 #[cfg(feature = "esp32s3")]
 #[allow(non_camel_case_types)]
 mod s3 {
-
     type spi_flash_func_t = unsafe extern "C" fn();
     type spi_flash_op_t = unsafe extern "C" fn() -> i32;
     type spi_flash_erase_t = unsafe extern "C" fn(u32) -> i32;
@@ -82,7 +81,6 @@ use s3::*;
 
 #[cfg(feature = "esp32s3")]
 extern "C" {
-
     static mut rom_spiflash_legacy_funcs: *const spiflash_legacy_funcs_t;
     static mut rom_spiflash_legacy_data: *mut ();
 

src/flash.rs

@@ -2,6 +2,8 @@
 #![no_main]
 #![cfg_attr(target_arch = "xtensa", feature(asm_experimental_arch))]
 
+// TODO: implement clock frequency setting for ESP32-C5
+
 // Target memory configuration
 
 // Decompressor is 43776 bytes, reserve more in case compiler changes layout
@@ -78,7 +80,6 @@ const ERROR_BASE_FLASH: i32 = -4000;
 
 #[cfg(feature = "log")]
 mod log {
-
     extern "C" {
         fn uart_tx_one_char(byte: u8);
     }
@@ -119,22 +120,138 @@ macro_rules! dprintln {
     ($fmt:expr, $($arg:tt)*) => {};
 }
 
+#[cfg(all(feature = "max-cpu-frequency", not(feature = "esp32c5")))]
+mod max_cpu_frequency {
+    cfg_if::cfg_if! {
+        if #[cfg(feature = "esp32")] {
+            const SYSTEM_CPU_PER_CONF_REG: *mut u32 = 0x3FF0003C as *mut u32;
+            const SYSTEM_CPUPERIOD_SEL_M: u32 = 3;
+            const SYSTEM_CPUPERIOD_MAX:   u32 = 2;
+
+            const SYSTEM_SYSCLK_CONF_REG: *mut u32 = 0x3FF48070 as *mut u32;
+            const SYSTEM_SOC_CLK_SEL_M: u32 = 3 << 27;
+            const SYSTEM_SOC_CLK_MAX:   u32 = 1 << 27;
+        } else if #[cfg(feature = "esp32s2")] {
+            const SYSTEM_CPU_PER_CONF_REG: *mut u32 = 0x3F4C0018 as *mut u32;
+            const SYSTEM_CPUPERIOD_SEL_M: u32 = 3;
+            const SYSTEM_CPUPERIOD_MAX:   u32 = 2;
+
+            const SYSTEM_SYSCLK_CONF_REG: *mut u32 = 0x3F4C008C as *mut u32;
+            const SYSTEM_SOC_CLK_SEL_M: u32 = 3 << 10;
+            const SYSTEM_SOC_CLK_MAX:   u32 = 1 << 10;
+        } else if #[cfg(feature = "esp32s3")] {
+            const SYSTEM_CPU_PER_CONF_REG: *mut u32 = 0x600C0010 as *mut u32;
+            const SYSTEM_CPUPERIOD_SEL_M: u32 = 3;
+            const SYSTEM_CPUPERIOD_MAX:   u32 = 2;
+
+            const SYSTEM_SYSCLK_CONF_REG: *mut u32 = 0x600C0060 as *mut u32;
+            const SYSTEM_SOC_CLK_SEL_M: u32 = 3 << 10;
+            const SYSTEM_SOC_CLK_MAX:   u32 = 1 << 10;
+        } else if #[cfg(any(feature = "esp32c2", feature = "esp32c3"))] {
+            const SYSTEM_CPU_PER_CONF_REG: *mut u32 = 0x600C0008 as *mut u32;
+            const SYSTEM_CPUPERIOD_SEL_M: u32 = 3;
+            const SYSTEM_CPUPERIOD_MAX:   u32 = 1;
+
+            const SYSTEM_SYSCLK_CONF_REG: *mut u32 = 0x600C0058 as *mut u32;
+            const SYSTEM_SOC_CLK_SEL_M: u32 = 3 << 10;
+            const SYSTEM_SOC_CLK_MAX:   u32 = 1 << 10;
+        } else if #[cfg(feature = "esp32h2")] {
+            const PCR_SYSCLK_CONF_REG: *mut u32 = 0x6009610c as *mut u32;
+
+            const PCR_SOC_CLK_SEL_M: u32 = 3 << 16;
+            const PCR_SOC_CLK_MAX: u32 = 1 << 16;
+        } else if #[cfg(feature = "esp32c6")] {
+            const PCR_SYSCLK_CONF_REG: *mut u32 = 0x60096110 as *mut u32;
+
+            const PCR_SOC_CLK_SEL_M: u32 = 3 << 16;
+            const PCR_SOC_CLK_MAX: u32 = 1 << 16;
+        }
+    }
+
+    pub struct CpuSaveState {
+        #[cfg(not(any(feature = "esp32c6", feature = "esp32h2")))]
+        saved_cpu_per_conf_reg: u32,
+        saved_sysclk_conf_reg: u32,
+    }
+
+    pub fn set_max_cpu_freq(state: &mut CpuSaveState) {
+        cfg_if::cfg_if! {
+            if #[cfg(any(feature = "esp32c6", feature = "esp32h2"))] {
+                state.saved_sysclk_conf_reg = unsafe { PCR_SYSCLK_CONF_REG.read_volatile() };
+            } else {
+                state.saved_cpu_per_conf_reg = unsafe { SYSTEM_CPU_PER_CONF_REG.read_volatile() };
+                state.saved_sysclk_conf_reg = unsafe { SYSTEM_SYSCLK_CONF_REG.read_volatile() };
+            }
+        }
+
+        cfg_if::cfg_if! {
+            if #[cfg(any(feature = "esp32c6", feature = "esp32h2"))] {
+                unsafe { PCR_SYSCLK_CONF_REG.write_volatile((state.saved_sysclk_conf_reg & !PCR_SOC_CLK_SEL_M) | PCR_SOC_CLK_MAX) };
+            } else if #[cfg(feature = "esp32s3")] {
+                extern "C" {
+                    fn ets_delay_us(us: u32);
+                }
+
+                unsafe { SYSTEM_SYSCLK_CONF_REG.write_volatile((state.saved_sysclk_conf_reg & !SYSTEM_SOC_CLK_SEL_M) | SYSTEM_SOC_CLK_MAX) };
+                  // Leave some time for the change to settle, needed for ESP32-S3
+                unsafe { ets_delay_us(100) };
+                unsafe { SYSTEM_CPU_PER_CONF_REG.write_volatile((state.saved_cpu_per_conf_reg & !SYSTEM_CPUPERIOD_SEL_M) | SYSTEM_CPUPERIOD_MAX) };
+            } else  {
+                unsafe { SYSTEM_CPU_PER_CONF_REG.write_volatile((state.saved_cpu_per_conf_reg & !SYSTEM_CPUPERIOD_SEL_M) | SYSTEM_CPUPERIOD_MAX) };
+                unsafe { SYSTEM_SYSCLK_CONF_REG.write_volatile((state.saved_sysclk_conf_reg & !SYSTEM_SOC_CLK_SEL_M) | SYSTEM_SOC_CLK_MAX) };
+            }
+        }
+    }
+
+    pub fn restore_max_cpu_freq(state: &mut CpuSaveState) {
+        cfg_if::cfg_if! {
+            if #[cfg(any(feature = "esp32c6", feature = "esp32h2"))] {
+                unsafe { PCR_SYSCLK_CONF_REG.write_volatile(state.saved_sysclk_conf_reg) };
+            } else {
+                unsafe { SYSTEM_SYSCLK_CONF_REG.write_volatile(state.saved_sysclk_conf_reg) };
+                unsafe { SYSTEM_CPU_PER_CONF_REG.write_volatile(state.saved_cpu_per_conf_reg) };
+            }
+        }
+    }
+}
+
+#[cfg(any(not(feature = "max-cpu-frequency"), feature = "esp32c5"))]
+mod max_cpu_frequency {
+    pub struct CpuSaveState {}
+
+    pub fn set_max_cpu_freq(_: &mut CpuSaveState) {}
+    pub fn restore_max_cpu_freq(_: &mut CpuSaveState) {}
+}
+
+use max_cpu_frequency::*;
+
+struct FlasherState {
+    inited: u32,
+    saved_cpu_state: CpuSaveState,
+    decompressor: Decompressor,
+}
+
 const INITED_MAGIC: u32 = 0xAAC0FFEE;
-const INITED: *mut u32 = STATE_ADDR as *mut u32;
-const DECOMPRESSOR: *mut Decompressor = (STATE_ADDR + 4) as *mut Decompressor;
+const STATE_OBJ: *mut FlasherState = STATE_ADDR as *mut FlasherState;
+
+fn state() -> &'static mut FlasherState {
+    unsafe { &mut *STATE_OBJ }
+}
 
 fn is_inited() -> bool {
-    unsafe { *INITED == INITED_MAGIC }
+    state().inited == INITED_MAGIC
 }
 
 /// Setup the device for the flashing process.
 #[no_mangle]
 pub unsafe extern "C" fn Init_impl(_adr: u32, _clk: u32, _fnc: u32) -> i32 {
     dprintln!("INIT");
 
+    set_max_cpu_freq(&mut state().saved_cpu_state);
+
     if flash::attach() == 0 {
-        *DECOMPRESSOR = Decompressor::new();
-        *INITED = INITED_MAGIC;
+        state().decompressor = Decompressor::new();
+        state().inited = INITED_MAGIC;
         0
     } else {
         1
@@ -175,7 +292,7 @@ pub unsafe extern "C" fn ProgramPage_impl(adr: u32, sz: u32, buf: *const u8) ->
 
     let input = core::slice::from_raw_parts(buf, sz as usize);
 
-    (*DECOMPRESSOR).program(adr, input)
+    state().decompressor.program(adr, input)
 }
 
 #[no_mangle]
@@ -193,7 +310,7 @@ pub unsafe extern "C" fn Verify_impl(adr: u32, sz: u32, buf: *const u8) -> i32 {
 
     let input = core::slice::from_raw_parts(buf, sz as usize);
 
-    (*DECOMPRESSOR).verify(adr, input)
+    state().decompressor.verify(adr, input)
 }
 
 #[no_mangle]
@@ -219,7 +336,8 @@ pub unsafe extern "C" fn UnInit_impl(fnc: u32) -> i32 {
         return ERROR_BASE_INTERNAL - 1;
     };
 
-    *INITED = 0;
+    restore_max_cpu_freq(&mut state().saved_cpu_state);
+    state().inited = 0;
 
     if fnc == 2 {
         // The flash ROM functions don't wait for the end of the last operation.