Tune flash loaders (#7)

* Add aliasses to simplify building

* Use block erase and bigger write page

Author: bugadani

.cargo/config.toml

@@ -1,4 +1,8 @@
-
+[alias]
+esp32c2 = "build --release --features esp32c2 --target riscv32imc-unknown-none-elf"
+esp32c3 = "build --release --features esp32c3 --target riscv32imc-unknown-none-elf"
+esp32c6 = "build --release --features esp32c6 --target riscv32imac-unknown-none-elf"
+esp32h2 = "build --release --features esp32h2 --target riscv32imac-unknown-none-elf"
 
 [target.'cfg(any(target_arch = "xtensa", target_arch = "riscv32"))']
 rustflags = [

README.md

@@ -5,21 +5,24 @@ A probe-rs flash loader for Espressif chips.
 To build the flash loader:
 
 ```bash
-$ cargo build --release --feature $(CHIP_NAME) --target $(RUST_TARGET) # builds the flashing stub
+$ cargo $(CHIP_NAME) # builds the flashing stub
 $ target-gen elf target/$(RUST_TARGET)/release/esp-flashloader output/$(CHIP_NAME).yaml --update --name $(CHIP_NAME)-flashloader
 ```
 
 Example for the updating the `esp32c3` flash algorithm.
 
 ```bash
-$ cargo build --release --features esp32c3 --target riscv32imc-unknown-none-elf
+$ cargo esp32c3
 $ target-gen elf target/riscv32imc-unknown-none-elf/release/esp-flashloader output/esp32c3.yaml --update --name esp32c3-flashloader
 ```
 
 ## Chip support
 
 | name    | supported |
 | ------- | --------- |
+| esp32   | N         |
+| esp32s2 | N         |
+| esp32s3 | N         |
 | esp32c2 | Y         |
 | esp32c3 | Y         |
 | esp32c6 | Y         |
@@ -28,8 +31,9 @@ $ target-gen elf target/riscv32imc-unknown-none-elf/release/esp-flashloader outp
 ## Adding new chips
 
 1. Add a feature for the chip inside `Cargo.toml`
-2. Add the [ROM API linker script](https://github.com/search?q=repo%3Aespressif%2Fesp-idf++path%3A*rom.api.ld&type=code) inside the `ld` directory.
-3. Inside the ROM API linker script, add a memory section detailing where the program will be loaded.
+2. Add a build alias to `.cargo/config.toml`
+3. Add the [ROM API linker script](https://github.com/search?q=repo%3Aespressif%2Fesp-idf++path%3A*rom.api.ld&type=code) inside the `ld` directory.
+4. Inside the ROM API linker script, add a memory section detailing where the program will be loaded.
     ```c
     MEMORY {
         /* Start 64k into the RAM region */
@@ -38,20 +42,20 @@ $ target-gen elf target/riscv32imc-unknown-none-elf/release/esp-flashloader outp
     ```
     It's important to note that the algorithm cannot be loaded at the start of RAM, because probe-rs has a header it loads prior to the algo hence the 64K offset.
     IRAM origin and length can be obtained from esp-hal. Eg: [ESP32-C3 memory map](https://github.com/esp-rs/esp-hal/blob/ff80b69183739d04d1cb154b8232be01c0b26fd9/esp32c3-hal/ld/db-esp32c3-memory.x#L5-L22)
-4. Add the following snippet to the `main()` function inside `build.rs`, adapting it for the new chip name.
+5. Add the following snippet to the `main()` function inside `build.rs`, adapting it for the new chip name.
     ```rust
     #[cfg(feature = "esp32c3")]
     let chip = "esp32c3";
     ```
-5. [Define `spiconfig` for your the target in `main.rs`](https://github.com/search?q=repo%3Aespressif%2Fesp-idf+ets_efuse_get_spiconfig+path%3A*c3*&type=code)
-6. Follow the instructions above for building
+6. [Define `spiconfig` for your the target in `main.rs`](https://github.com/search?q=repo%3Aespressif%2Fesp-idf+ets_efuse_get_spiconfig+path%3A*c3*&type=code)
+7. Follow the instructions above for building
   - It may fail with: `rust-lld: error: undefined symbol: <symbol>`
     - In this case, you need to add the missing method in the ROM API linker script.
       - Eg. ESP32-C2 is missing `esp_rom_spiflash_attach`:
         1. [Search the symbol in esp-idf](https://github.com/search?q=repo%3Aespressif%2Fesp-idf+esp_rom_spiflash_attach+path%3A*c2*&type=code)
         2. Add it to the ROM API linker script: `PROVIDE(esp_rom_spiflash_attach = spi_flash_attach);`
-7. Use `target-gen` _without_ the `update` flag to generate a new yaml algorithm.
-8. Update the resulting yaml file
+8. Use `target-gen` _without_ the `update` flag to generate a new yaml algorithm.
+9. Update the resulting yaml file
    1. Update `name`
    2. Update variants `name`, `type`, `core_access_options` and `memory_map`
       - The first `!Nvm`  block represents the raw flash starting at 0 and up to the maximum supported external flash (check TRM for this, usually in "System and Memory/Features")

src/main.rs

@@ -9,7 +9,7 @@
 
 use panic_never as _;
 
-const FLASH_SECTOR_SIZE: u32 = 4096;
+const FLASH_BLOCK_SIZE: u32 = 65536;
 
 #[cfg(not(any(target_arch = "xtensa", target_arch = "riscv32")))]
 compile_error!("specify the target with `--target`");
@@ -54,12 +54,10 @@ macro_rules! dprintln {
 #[allow(unused)]
 extern "C" {
 
-    // fn esp_rom_spiflash_wait_idle(/* esp_rom_spiflash_chip_t *spi */);
     // fn esp_rom_spiflash_write_encrypted_enable();
     // fn esp_rom_spiflash_write_encrypted_disable();
     // fn esp_rom_spiflash_write_encrypted(addr: u32, data: *const u8, len: u32);
     // fn esp_rom_spiflash_config_param();
-    // fn esp_rom_spiflash_read_user_cmd();
     // fn esp_rom_spiflash_select_qio_pins();
     // fn esp_rom_spi_flash_auto_sus_res();
     // fn esp_rom_spi_flash_send_resume();
@@ -77,6 +75,7 @@ extern "C" {
     fn esp_rom_spiflash_write(dest_addr: u32, data: *const u8, len: u32) -> i32;
     /// address (4 byte alignment), data, length
     fn esp_rom_spiflash_read(src_addr: u32, data: *const u32, len: u32) -> i32;
+    fn esp_rom_spiflash_read_user_cmd(status: *mut u32, cmd: u8) -> i32;
     fn esp_rom_spiflash_unlock() -> i32;
     // fn esp_rom_spiflash_lock(); // can't find in idf defs?
     fn esp_rom_spiflash_attach(config: u32, legacy: bool);
@@ -87,6 +86,20 @@ extern "C" {
 
 }
 
+unsafe fn wait_for_idle() -> i32 {
+    const SR_WIP: u32 = 1 << 0;
+
+    let mut status = SR_WIP;
+    while status & SR_WIP != 0 {
+        let res = esp_rom_spiflash_read_user_cmd(&mut status, 0x05);
+        if res != 0 {
+            return res;
+        }
+    }
+
+    0
+}
+
 /// Setup the device for the
 #[no_mangle]
 #[inline(never)]
@@ -103,11 +116,6 @@ pub unsafe extern "C" fn Init(_adr: u32, _clk: u32, _fnc: u32) -> i32 {
 
         esp_rom_spiflash_attach(spiconfig, false);
 
-        let res = esp_rom_spiflash_unlock();
-        if res != 0 {
-            return res;
-        }
-
         INITD = true;
     }
 
@@ -121,12 +129,7 @@ pub unsafe extern "C" fn Init(_adr: u32, _clk: u32, _fnc: u32) -> i32 {
 #[inline(never)]
 pub unsafe extern "C" fn EraseSector(adr: u32) -> i32 {
     dprintln!("ERASE @ {}", adr);
-    let res = esp_rom_spiflash_erase_sector(adr / FLASH_SECTOR_SIZE);
-    if res != 0 {
-        return res;
-    }
-
-    0
+    esp_rom_spiflash_erase_block(adr / FLASH_BLOCK_SIZE)
 }
 
 #[no_mangle]
@@ -146,18 +149,13 @@ pub unsafe extern "C" fn ProgramPage(adr: u32, sz: u32, buf: *const u8) -> i32 {
 
     dprintln!("PROGRAM {} bytes @ {}", sz, adr);
 
-    let res = esp_rom_spiflash_write(adr, buf, sz);
-    if res != 0 {
-        return res;
-    }
-
-    0
+    esp_rom_spiflash_write(adr, buf, sz)
 }
 
 #[no_mangle]
 #[inline(never)]
-pub extern "C" fn UnInit(_fnc: u32) -> i32 {
-    0
+pub unsafe extern "C" fn UnInit(_fnc: u32) -> i32 {
+    wait_for_idle()
 }
 
 #[allow(non_upper_case_globals)]
@@ -171,7 +169,7 @@ pub static FlashDevice: FlashDeviceDescription = FlashDeviceDescription {
     dev_addr: 0x0,
     device_size: 0x4000000, /* Max of 64MB */
     // TODO change per variant?
-    page_size: 2048,
+    page_size: 16384,
     _reserved: 0,
     empty: 0xFF,
     program_time_out: 1000,
@@ -188,7 +186,7 @@ const fn sectors() -> [FlashSector; 512] {
     let mut sectors = [FlashSector::default(); 512];
 
     sectors[0] = FlashSector {
-        size: 0x1000, // 4k
+        size: 0x10000, // 64k
         address: 0x0,
     };
     sectors[1] = SECTOR_END;