esp32p4: use only up to bank 3

Banks 4 and 5 appear to be unavailable when booting fresh out of the stage 1
bootloader.

Signed-off-by: Sean Cross <sean@xobs.io>

Author: xobs

ld/esp32p4.x

@@ -5,6 +5,7 @@ MEMORY {
 }
 
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
+PROVIDE ( uart_tx_one_char = usb_serial_device_tx_one_char );
 
 /*
  * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
@@ -41,7 +42,7 @@ ets_update_cpu_frequency = 0x4fc00044;
 ets_install_lock = 0x4fc00048;
 UartRxString = 0x4fc0004c;
 UartGetCmdLn = 0x4fc00050;
-uart_tx_one_char = 0x4fc00054;
+/*uart_tx_one_char = 0x4fc00054;*/
 uart_tx_one_char2 = 0x4fc00058;
 uart_tx_one_char3 = 0x4fc0005c;
 uart_rx_one_char = 0x4fc00060;

src/main.rs

@@ -33,7 +33,7 @@ const _: [u8; 43776] = [0; core::mem::size_of::<Decompressor>()];
 // ESP32-C6  | 0x4081_0000 | 0x4081_0000 | 0x4084_0000 | 0x4085_0000    | 0x4086_0000
 // ESP32-C61 | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000    | 0x4083_8000 !! ROM data use starts at 0x4083EA70, so let's use H2's memory layout
 // ESP32-H2  | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000    | 0x4083_8000 !! has smaller RAM, only reserve 32K for data
-// ESP32-P4  | 0x4FF1_0000 | 0x4FF1_0000 | 0x4FFA_0000 | 0x4FFB_0000    | 0x4FFC_0000
+// ESP32-P4  | 0x4FF1_0000 | 0x4FF1_0000 | 0x4FF6_0000 | 0x4FF7_0000    | 0x4FFC_0000
 
 // "State" base address
 #[cfg(feature = "esp32")]
@@ -55,7 +55,7 @@ const STATE_ADDR: usize = 0x4082_0000;
 #[cfg(feature = "esp32h2")]
 const STATE_ADDR: usize = 0x4082_0000;
 #[cfg(feature = "esp32p4")]
-const STATE_ADDR: usize = 0x4FFA_0000;
+const STATE_ADDR: usize = 0x4FF6_0000;
 
 // End of target memory configuration