shift memory range up to 0x8ff40020

xobs · xobs · commit 42a87336335d · 2025-11-22T23:36:57.000+08:00
diff --git a/ld/esp32p4.x b/ld/esp32p4.x
@@ -1,7 +1,7 @@
 
 MEMORY {
-    /* Start 64k into the uncached RAM region */
-    IRAM : ORIGIN = 0x8FF30000, LENGTH = 0x10000
+    /* Start 256k into the uncached RAM region */
+    IRAM : ORIGIN = 0x8FF50000, LENGTH = 0x10000
 }
 
 PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
diff --git a/src/main.rs b/src/main.rs
@@ -33,7 +33,7 @@ const _: [u8; 43776] = [0; core::mem::size_of::<Decompressor>()];
 // ESP32-C6  | 0x4081_0000 | 0x4081_0000 | 0x4084_0000 | 0x4085_0000    | 0x4086_0000
 // ESP32-C61 | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000    | 0x4083_8000 !! ROM data use starts at 0x4083EA70, so let's use H2's memory layout
 // ESP32-H2  | 0x4081_0000 | 0x4081_0000 | 0x4082_0000 | 0x4083_0000    | 0x4083_8000 !! has smaller RAM, only reserve 32K for data
-// ESP32-P4  | 0x8FF3_0000 | 0x8FF3_0000 | 0x8FF6_0000 | 0x8FF7_0000    | 0x8FFC_0000 !! Uncached region
+// ESP32-P4  | 0x8FF4_0020 | 0x8FF4_0020 | 0x8FF6_0000 | 0x8FF7_0000    | 0x8FFC_0000 !! Uncached region
 
 // "State" base address
 #[cfg(feature = "esp32")]

Original file line number	Diff line number	Diff line change
`@@ -1,7 +1,7 @@`
`1`	`1`
`2`	`2`	`MEMORY {`
`3`		`- /* Start 64k into the uncached RAM region */`
`4`		`- IRAM : ORIGIN = 0x8FF30000, LENGTH = 0x10000`
	`3`	`+ /* Start 256k into the uncached RAM region */`
	`4`	`+ IRAM : ORIGIN = 0x8FF50000, LENGTH = 0x10000`
`5`	`5`	`}`
`6`	`6`
`7`	`7`	`PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );`