Inflate miniz-compressed stream (#11)

* Decompress a deflated stream using tinfl

* Clean up

* Add instruction to readme

Author: bugadani

README.md

@@ -63,5 +63,6 @@ $ target-gen elf target/riscv32imc-unknown-none-elf/release/esp-flashloader outp
       - Next `!Ram` block corresponds to data bus for internal SRAM, see Internal Memory Address Mapping of TRM
       - Next `!Nvm` corresponds to instruction bus for external memory, see External Memory Address Mapping of TRM
       - Next `!Nvm` corresponds to data bus for external memory, see External Memory Address Mapping of TRM
-   3. Add `load_address` under `flash_algorithms` and assing the IRAM `ORIGIN` value (step 3).
+   3. Add `load_address` under `flash_algorithms` and assign the IRAM `ORIGIN` value (step 3).
+   4. Add `transfer_encoding: Miniz` under `load_address`
 9. Upstream the new updates to probe-rs.

ld/esp32c3.x

@@ -82,4 +82,27 @@ PROVIDE( Enable_QMode = 0x40000228 );
 PROVIDE( ets_efuse_get_spiconfig = 0x4000071c );
 
 
-PROVIDE( uart_tx_one_char = 0x40000068 );
+PROVIDE( uart_tx_one_char = 0x40000068 );
+
+/***************************************
+ Group miniz
+ ***************************************/
+
+/* Functions */
+mz_adler32 = 0x400000c0;
+mz_crc32 = 0x400000c4;
+mz_free = 0x400000c8;
+tdefl_compress = 0x400000cc;
+tdefl_compress_buffer = 0x400000d0;
+tdefl_compress_mem_to_heap = 0x400000d4;
+tdefl_compress_mem_to_mem = 0x400000d8;
+tdefl_compress_mem_to_output = 0x400000dc;
+tdefl_get_adler32 = 0x400000e0;
+tdefl_get_prev_return_status = 0x400000e4;
+tdefl_init = 0x400000e8;
+tdefl_write_image_to_png_file_in_memory = 0x400000ec;
+tdefl_write_image_to_png_file_in_memory_ex = 0x400000f0;
+tinfl_decompress = 0x400000f4;
+tinfl_decompress_mem_to_callback = 0x400000f8;
+tinfl_decompress_mem_to_heap = 0x400000fc;
+tinfl_decompress_mem_to_mem = 0x40000100;

ld/loader.x

@@ -26,13 +26,12 @@ SECTIONS {
 
         *(.bss .bss.*)
         *(.sbss .sbss.*)
-        
+
         . = ALIGN(4);
     } > IRAM
 
     /* Description of the flash algorithm */
-    DeviceData : 
-    {
+    DeviceData : {
         /* The device data content is only for external tools,
          * and usually not referenced by the code.
          *

src/flash.rs

@@ -0,0 +1,74 @@
+extern "C" {
+
+    // fn esp_rom_spiflash_write_encrypted_enable();
+    // fn esp_rom_spiflash_write_encrypted_disable();
+    // fn esp_rom_spiflash_write_encrypted(addr: u32, data: *const u8, len: u32);
+    // fn esp_rom_spiflash_config_param();
+    // fn esp_rom_spiflash_select_qio_pins();
+    // fn esp_rom_spi_flash_auto_sus_res();
+    // fn esp_rom_spi_flash_send_resume();
+    // fn esp_rom_spi_flash_update_id();
+    // fn esp_rom_spiflash_config_clk();
+    // fn esp_rom_spiflash_config_readmode();
+    // fn esp_rom_spiflash_read_status(/* esp_rom_spiflash_chip_t *spi ,*/ status: *mut u32);
+    // fn esp_rom_spiflash_read_statushigh(/* esp_rom_spiflash_chip_t *spi ,*/ status: *mut u32);
+    // fn esp_rom_spiflash_write_status(/* esp_rom_spiflash_chip_t *spi ,*/ status: *mut u32);
+
+    fn esp_rom_spiflash_erase_chip() -> i32;
+    fn esp_rom_spiflash_erase_block(block_number: u32) -> i32;
+    // fn esp_rom_spiflash_erase_sector(sector_number: u32) -> i32;
+    /// address (4 byte alignment), data, length
+    fn esp_rom_spiflash_write(dest_addr: u32, data: *const u8, len: u32) -> i32;
+    /// address (4 byte alignment), data, length
+    // fn esp_rom_spiflash_read(src_addr: u32, data: *const u32, len: u32) -> i32;
+    fn esp_rom_spiflash_read_user_cmd(status: *mut u32, cmd: u8) -> i32;
+    // fn esp_rom_spiflash_unlock() -> i32;
+    // fn esp_rom_spiflash_lock(); // can't find in idf defs?
+    fn esp_rom_spiflash_attach(config: u32, legacy: bool);
+
+    #[cfg(feature = "esp32c3")]
+    fn ets_efuse_get_spiconfig() -> u32;
+}
+
+pub fn attach() {
+    #[cfg(feature = "esp32c3")]
+    let spiconfig: u32 = unsafe { ets_efuse_get_spiconfig() };
+    #[cfg(any(feature = "esp32c2", feature = "esp32c6", feature = "esp32h2"))]
+    let spiconfig: u32 = 0;
+
+    // TODO: raise CPU frequency
+
+    unsafe { esp_rom_spiflash_attach(spiconfig, false) };
+}
+
+pub fn erase_block(adr: u32) -> i32 {
+    crate::dprintln!("ERASE @ {}", adr);
+
+    unsafe { esp_rom_spiflash_erase_block(adr / crate::properties::FLASH_BLOCK_SIZE) }
+}
+
+pub fn erase_chip() -> i32 {
+    unsafe { esp_rom_spiflash_erase_chip() }
+}
+
+pub fn write_flash(address: u32, data: &[u8]) -> i32 {
+    if data.is_empty() {
+        return 0;
+    }
+    let len = data.len() as u32;
+    unsafe { esp_rom_spiflash_write(address, data.as_ptr(), len) }
+}
+
+pub fn wait_for_idle() -> i32 {
+    const SR_WIP: u32 = 1 << 0;
+
+    let mut status = SR_WIP;
+    while status & SR_WIP != 0 {
+        let res = unsafe { esp_rom_spiflash_read_user_cmd(&mut status, 0x05) };
+        if res != 0 {
+            return res;
+        }
+    }
+
+    0
+}