@@ -126,6 +126,20 @@ static const struct _coeff_div coeff_div[] = {
126126 {3072000 , 24000 , 0x01 , 0x02 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
127127 {1536000 , 24000 , 0x01 , 0x04 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
128128
129+ /* 26390 */
130+ {11289600 , 26390 , 0x03 , 0x01 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
131+ {6818048 , 26390 , 0x01 , 0x08 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
132+ {5644800 , 26390 , 0x01 , 0x01 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
133+ {2822400 , 26390 , 0x01 , 0x02 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
134+ {1411200 , 26390 , 0x01 , 0x04 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
135+
136+ /* 26633 */
137+ {11289600 , 26633 , 0x03 , 0x01 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
138+ {6818048 , 26633 , 0x01 , 0x08 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
139+ {5644800 , 26633 , 0x01 , 0x01 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
140+ {2822400 , 26633 , 0x01 , 0x02 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
141+ {1411200 , 26633 , 0x01 , 0x04 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
142+
129143 /* 32k */
130144 {12288000 , 32000 , 0x03 , 0x02 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
131145 {18432000 , 32000 , 0x03 , 0x04 , 0x03 , 0x03 , 0x00 , 0x02 , 0xff , 0x0c , 0x10 , 0x10 },
@@ -138,6 +152,16 @@ static const struct _coeff_div coeff_div[] = {
138152 {1536000 , 32000 , 0x03 , 0x08 , 0x01 , 0x01 , 0x01 , 0x00 , 0x7f , 0x02 , 0x10 , 0x10 },
139153 {1024000 , 32000 , 0x01 , 0x08 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
140154
155+ /* 32768 */
156+ {12288000 , 32768 , 0x03 , 0x02 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
157+ {18432000 , 32768 , 0x03 , 0x04 , 0x03 , 0x03 , 0x00 , 0x02 , 0xff , 0x0c , 0x10 , 0x10 },
158+ {16384000 , 32768 , 0x02 , 0x01 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
159+ {8388608 , 32768 , 0x01 , 0x01 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
160+ {8192000 , 32768 , 0x01 , 0x01 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
161+ {6144000 , 32768 , 0x03 , 0x04 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
162+ {4096000 , 32768 , 0x01 , 0x02 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
163+ {3072000 , 32768 , 0x03 , 0x08 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
164+
141165 /* 44.1k */
142166 {11289600 , 44100 , 0x01 , 0x01 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
143167 {5644800 , 44100 , 0x01 , 0x02 , 0x01 , 0x01 , 0x00 , 0x00 , 0xff , 0x04 , 0x10 , 0x10 },
@@ -340,7 +364,7 @@ esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg) {
340364 return ESP_FAIL;
341365 }
342366 /*
343- * Set clock parammeters
367+ * Set clock parameters
344368 */
345369 regv = es8311_read_reg (ES8311_CLK_MANAGER_REG02) & 0x07 ;
346370 regv |= (coeff_div[coeff].pre_div - 1 ) << 5 ;
@@ -430,6 +454,77 @@ esp_err_t es8311_codec_init(audio_hal_codec_config_t *codec_cfg) {
430454 return ESP_OK;
431455}
432456
457+ esp_err_t es8311_codec_set_sample_rate (int sample_rate) {
458+ esp_err_t ret = ESP_OK;
459+ int sample_fre = sample_rate;
460+ int mclk_fre = sample_fre * MCLK_DIV_FRE;
461+ int coeff = get_coeff (mclk_fre, sample_fre);
462+ if (coeff < 0 ) {
463+ ESP_LOGE (TAG, " Unable to configure sample rate %dHz with %dHz MCLK" , sample_fre, mclk_fre);
464+ return ESP_FAIL;
465+ }
466+ /*
467+ * Set clock parameters
468+ */
469+ uint8_t regv = es8311_read_reg (ES8311_CLK_MANAGER_REG02) & 0x07 ;
470+ regv |= (coeff_div[coeff].pre_div - 1 ) << 5 ;
471+ uint8_t datmp = 0 ;
472+ switch (coeff_div[coeff].pre_multi ) {
473+ case 1 :
474+ datmp = 0 ;
475+ break ;
476+ case 2 :
477+ datmp = 1 ;
478+ break ;
479+ case 4 :
480+ datmp = 2 ;
481+ break ;
482+ case 8 :
483+ datmp = 3 ;
484+ break ;
485+ default :
486+ break ;
487+ }
488+
489+ if (ES8311_MCLK_SOURCE == FROM_SCLK_PIN) {
490+ datmp = 3 ; /* DIG_MCLK = LRCK * 256 = BCLK * 8 */
491+ }
492+ regv |= (datmp) << 3 ;
493+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG02, regv);
494+
495+ regv = es8311_read_reg (ES8311_CLK_MANAGER_REG05) & 0x00 ;
496+ regv |= (coeff_div[coeff].adc_div - 1 ) << 4 ;
497+ regv |= (coeff_div[coeff].dac_div - 1 ) << 0 ;
498+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG05, regv);
499+
500+ regv = es8311_read_reg (ES8311_CLK_MANAGER_REG03) & 0x80 ;
501+ regv |= coeff_div[coeff].fs_mode << 6 ;
502+ regv |= coeff_div[coeff].adc_osr << 0 ;
503+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG03, regv);
504+
505+ regv = es8311_read_reg (ES8311_CLK_MANAGER_REG04) & 0x80 ;
506+ regv |= coeff_div[coeff].dac_osr << 0 ;
507+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG04, regv);
508+
509+ regv = es8311_read_reg (ES8311_CLK_MANAGER_REG07) & 0xC0 ;
510+ regv |= coeff_div[coeff].lrck_h << 0 ;
511+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG07, regv);
512+
513+ regv = es8311_read_reg (ES8311_CLK_MANAGER_REG08) & 0x00 ;
514+ regv |= coeff_div[coeff].lrck_l << 0 ;
515+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG08, regv);
516+
517+ regv = es8311_read_reg (ES8311_CLK_MANAGER_REG06) & 0xE0 ;
518+ if (coeff_div[coeff].bclk_div < 19 ) {
519+ regv |= (coeff_div[coeff].bclk_div - 1 ) << 0 ;
520+ } else {
521+ regv |= (coeff_div[coeff].bclk_div ) << 0 ;
522+ }
523+ ret |= es8311_write_reg (ES8311_CLK_MANAGER_REG06, regv);
524+
525+ return ret;
526+ }
527+
433528esp_err_t es8311_codec_deinit () { return ESP_OK; }
434529
435530esp_err_t es8311_config_fmt (es_i2s_fmt_t fmt) {
0 commit comments