arch-riscv: Add RVV support for riscv32 ISA (gem5#2337)

Previous version configure the mstatus and misa only in riscv64, illegal
instruction exception occurs when simulate workload which compiled as
riscv-32 target, this commit set the CSR once 'enable_rvv' is true

Test: run scons build/RISCV/unittests.opt

Author: zhongchengyong

src/arch/riscv/isa.cc

@@ -403,10 +403,6 @@ void ISA::clear()
         case RV64:
           misa.rv64_mxl = 2;
           status.uxl = status.sxl = 2;
-          if (getEnableRvv()) {
-              status.vs = VPUStatus::INITIAL;
-              misa.rvv = 1;
-          }
           if (misa.rvh) {
               HSTATUS hstatus = 0;
               hstatus.vsxl = 2;
@@ -425,6 +421,10 @@ void ISA::clear()
         default:
           panic("%s: Unknown _rvType: %d", name(), (int)_rvType);
     }
+    if (getEnableRvv()) {
+        status.vs = VPUStatus::INITIAL;
+        misa.rvv = 1;
+    }
 
     miscRegFile[MISCREG_ISA] = misa;
     miscRegFile[MISCREG_STATUS] = status;