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GWTINYCGWTINYC
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11.19第2批补全
1 parent ba00c51 commit 43973b2

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2 files changed

+258
-48
lines changed

2 files changed

+258
-48
lines changed

‎library/stdarch/crates/core_arch/src/aarch64/sve/sve.rs‎

Lines changed: 210 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4764,6 +4764,216 @@ pub fn svmul_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t
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pub fn svmul_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
47654765
svmul_u64_z(pg, op1, svdup_n_u64(op2))
47664766
}
4767+
#[doc = "Reciprocal estimate"]
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#[doc = ""]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f32])"]
4770+
#[inline]
4771+
#[target_feature(enable = "sve")]
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#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4773+
#[cfg_attr(test, assert_instr(frecpe))]
4774+
pub fn svrecpe_f32(op: svfloat32_t) -> svfloat32_t {
4775+
unsafe extern "C" {
4776+
#[cfg_attr(
4777+
target_arch = "aarch64",
4778+
link_name = "llvm.aarch64.sve.frecpe.x.nxv4f32"
4779+
)]
4780+
fn _svrecpe_f32(op: svfloat32_t) -> svfloat32_t;
4781+
}
4782+
unsafe { _svrecpe_f32(op) }
4783+
}
4784+
#[doc = "Reciprocal estimate"]
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#[doc = ""]
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#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpe[_f64])"]
4787+
#[inline]
4788+
#[target_feature(enable = "sve")]
4789+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4790+
#[cfg_attr(test, assert_instr(frecpe))]
4791+
pub fn svrecpe_f64(op: svfloat64_t) -> svfloat64_t {
4792+
unsafe extern "C" {
4793+
#[cfg_attr(
4794+
target_arch = "aarch64",
4795+
link_name = "llvm.aarch64.sve.frecpe.x.nxv2f64"
4796+
)]
4797+
fn _svrecpe_f64(op: svfloat64_t) -> svfloat64_t;
4798+
}
4799+
unsafe { _svrecpe_f64(op) }
4800+
}
4801+
#[doc = "Reciprocal step"]
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#[doc = ""]
4803+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f32])"]
4804+
#[inline]
4805+
#[target_feature(enable = "sve")]
4806+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4807+
#[cfg_attr(test, assert_instr(frecps))]
4808+
pub fn svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
4809+
unsafe extern "C" {
4810+
#[cfg_attr(
4811+
target_arch = "aarch64",
4812+
link_name = "llvm.aarch64.sve.frecps.x.nxv4f32"
4813+
)]
4814+
fn _svrecps_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
4815+
}
4816+
unsafe { _svrecps_f32(op1, op2) }
4817+
}
4818+
#[doc = "Reciprocal step"]
4819+
#[doc = ""]
4820+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecps[_f64])"]
4821+
#[inline]
4822+
#[target_feature(enable = "sve")]
4823+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4824+
#[cfg_attr(test, assert_instr(frecps))]
4825+
pub fn svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
4826+
unsafe extern "C" {
4827+
#[cfg_attr(
4828+
target_arch = "aarch64",
4829+
link_name = "llvm.aarch64.sve.frecps.x.nxv2f64"
4830+
)]
4831+
fn _svrecps_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
4832+
}
4833+
unsafe { _svrecps_f64(op1, op2) }
4834+
}
4835+
#[doc = "Reciprocal exponent"]
4836+
#[doc = ""]
4837+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_m)"]
4838+
#[inline]
4839+
#[target_feature(enable = "sve")]
4840+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4841+
#[cfg_attr(test, assert_instr(frecpx))]
4842+
pub fn svrecpx_f32_m(inactive: svfloat32_t, pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
4843+
unsafe extern "C" {
4844+
#[cfg_attr(
4845+
target_arch = "aarch64",
4846+
link_name = "llvm.aarch64.sve.frecpx.x.nxv4f32"
4847+
)]
4848+
fn _svrecpx_f32_m(inactive: svfloat32_t, pg: svbool4_t, op: svfloat32_t) -> svfloat32_t;
4849+
}
4850+
unsafe { _svrecpx_f32_m(inactive, simd_cast(pg), op) }
4851+
}
4852+
#[doc = "Reciprocal exponent"]
4853+
#[doc = ""]
4854+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_x)"]
4855+
#[inline]
4856+
#[target_feature(enable = "sve")]
4857+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4858+
#[cfg_attr(test, assert_instr(frecpx))]
4859+
pub fn svrecpx_f32_x(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
4860+
svrecpx_f32_m(op, pg, op)
4861+
}
4862+
#[doc = "Reciprocal exponent"]
4863+
#[doc = ""]
4864+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f32]_z)"]
4865+
#[inline]
4866+
#[target_feature(enable = "sve")]
4867+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4868+
#[cfg_attr(test, assert_instr(frecpx))]
4869+
pub fn svrecpx_f32_z(pg: svbool_t, op: svfloat32_t) -> svfloat32_t {
4870+
svrecpx_f32_m(svdup_n_f32(0.0), pg, op)
4871+
}
4872+
#[doc = "Reciprocal exponent"]
4873+
#[doc = ""]
4874+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_m)"]
4875+
#[inline]
4876+
#[target_feature(enable = "sve")]
4877+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4878+
#[cfg_attr(test, assert_instr(frecpx))]
4879+
pub fn svrecpx_f64_m(inactive: svfloat64_t, pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
4880+
unsafe extern "C" {
4881+
#[cfg_attr(
4882+
target_arch = "aarch64",
4883+
link_name = "llvm.aarch64.sve.frecpx.x.nxv2f64"
4884+
)]
4885+
fn _svrecpx_f64_m(inactive: svfloat64_t, pg: svbool2_t, op: svfloat64_t) -> svfloat64_t;
4886+
}
4887+
unsafe { _svrecpx_f64_m(inactive, simd_cast(pg), op) }
4888+
}
4889+
#[doc = "Reciprocal exponent"]
4890+
#[doc = ""]
4891+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_x)"]
4892+
#[inline]
4893+
#[target_feature(enable = "sve")]
4894+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4895+
#[cfg_attr(test, assert_instr(frecpx))]
4896+
pub fn svrecpx_f64_x(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
4897+
svrecpx_f64_m(op, pg, op)
4898+
}
4899+
#[doc = "Reciprocal exponent"]
4900+
#[doc = ""]
4901+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrecpx[_f64]_z)"]
4902+
#[inline]
4903+
#[target_feature(enable = "sve")]
4904+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4905+
#[cfg_attr(test, assert_instr(frecpx))]
4906+
pub fn svrecpx_f64_z(pg: svbool_t, op: svfloat64_t) -> svfloat64_t {
4907+
svrecpx_f64_m(svdup_n_f64(0.0), pg, op)
4908+
}
4909+
#[doc = "Reciprocal square root estimate"]
4910+
#[doc = ""]
4911+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f32])"]
4912+
#[inline]
4913+
#[target_feature(enable = "sve")]
4914+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4915+
#[cfg_attr(test, assert_instr(frsqrte))]
4916+
pub fn svrsqrte_f32(op: svfloat32_t) -> svfloat32_t {
4917+
unsafe extern "C" {
4918+
#[cfg_attr(
4919+
target_arch = "aarch64",
4920+
link_name = "llvm.aarch64.sve.frsqrte.x.nxv4f32"
4921+
)]
4922+
fn _svrsqrte_f32(op: svfloat32_t) -> svfloat32_t;
4923+
}
4924+
unsafe { _svrsqrte_f32(op) }
4925+
}
4926+
#[doc = "Reciprocal square root estimate"]
4927+
#[doc = ""]
4928+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrte[_f64])"]
4929+
#[inline]
4930+
#[target_feature(enable = "sve")]
4931+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4932+
#[cfg_attr(test, assert_instr(frsqrte))]
4933+
pub fn svrsqrte_f64(op: svfloat64_t) -> svfloat64_t {
4934+
unsafe extern "C" {
4935+
#[cfg_attr(
4936+
target_arch = "aarch64",
4937+
link_name = "llvm.aarch64.sve.frsqrte.x.nxv2f64"
4938+
)]
4939+
fn _svrsqrte_f64(op: svfloat64_t) -> svfloat64_t;
4940+
}
4941+
unsafe { _svrsqrte_f64(op) }
4942+
}
4943+
#[doc = "Reciprocal square root step"]
4944+
#[doc = ""]
4945+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f32])"]
4946+
#[inline]
4947+
#[target_feature(enable = "sve")]
4948+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4949+
#[cfg_attr(test, assert_instr(frsqrts))]
4950+
pub fn svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t {
4951+
unsafe extern "C" {
4952+
#[cfg_attr(
4953+
target_arch = "aarch64",
4954+
link_name = "llvm.aarch64.sve.frsqrts.x.nxv4f32"
4955+
)]
4956+
fn _svrsqrts_f32(op1: svfloat32_t, op2: svfloat32_t) -> svfloat32_t;
4957+
}
4958+
unsafe { _svrsqrts_f32(op1, op2) }
4959+
}
4960+
#[doc = "Reciprocal square root step"]
4961+
#[doc = ""]
4962+
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svrsqrts[_f64])"]
4963+
#[inline]
4964+
#[target_feature(enable = "sve")]
4965+
#[unstable(feature = "stdarch_aarch64_sve", issue = "none")]
4966+
#[cfg_attr(test, assert_instr(frsqrts))]
4967+
pub fn svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t {
4968+
unsafe extern "C" {
4969+
#[cfg_attr(
4970+
target_arch = "aarch64",
4971+
link_name = "llvm.aarch64.sve.frsqrts.x.nxv2f64"
4972+
)]
4973+
fn _svrsqrts_f64(op1: svfloat64_t, op2: svfloat64_t) -> svfloat64_t;
4974+
}
4975+
unsafe { _svrsqrts_f64(op1, op2) }
4976+
}
47674977
#[doc = "Bitwise inclusive OR"]
47684978
#[doc = ""]
47694979
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svorr[_s8]_m)"]

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