diff --git a/Log/ITM0.log.csv b/Log/ITM0.log.csv new file mode 100644 index 0000000..7c23e17 --- /dev/null +++ b/Log/ITM0.log.csv @@ -0,0 +1,36 @@ +Event, Time (sec), Component, Event Property, Value, Overflow +0, 0.00031756, EvCtrl, EventRecorderInitialize, Restart Count = 1, no +1, 0.00031993, EvCtrl, EventRecorderStart, , no +2, 0.00032948, STDIO, stdout, 0x73 0x65 0x74 0x55 0x70 0x20 0x6D 0x79, no +3, 0.00033731, STDIO, stdout, 0x5F 0x74 0x65 0x73 0x74 0x0A 0x00 0x00, no +4, 0.00034806, STDIO, stdout, 0x74 0x65 0x61 0x72 0x44 0x6F 0x77 0x6E, no +5, 0.00035734, STDIO, stdout, 0x20 0x6D 0x79 0x5F 0x74 0x65 0x73 0x74, no +6, 0.00036151, STDIO, stdout, 0x0A 0x00 0x00 0x00 0x00 0x00 0x00 0x00, no +7, 0.00037250, STDIO, stdout, 0x2E 0x2E 0x5C 0x54 0x65 0x73 0x74 0x5C, no +8, 0.00038297, STDIO, stdout, 0x6D 0x79 0x5F 0x74 0x65 0x73 0x74 0x2E, no +9, 0.00039397, STDIO, stdout, 0x63 0x3A 0x31 0x33 0x3A 0x74 0x65 0x73, no +10, 0.00040444, STDIO, stdout, 0x74 0x57 0x69 0x6C 0x6C 0x41 0x6C 0x77, no +11, 0.00041488, STDIO, stdout, 0x61 0x79 0x73 0x50 0x61 0x73 0x73 0x3A, no +12, 0.00042294, STDIO, stdout, 0x50 0x41 0x53 0x53 0x0A 0x00 0x00 0x00, no +13, 0.00043299, STDIO, stdout, 0x73 0x65 0x74 0x55 0x70 0x20 0x6D 0x79, no +14, 0.00044081, STDIO, stdout, 0x5F 0x74 0x65 0x73 0x74 0x0A 0x00 0x00, no +15, 0.00045226, STDIO, stdout, 0x2E 0x2E 0x5C 0x54 0x65 0x73 0x74 0x5C, no +16, 0.00046273, STDIO, stdout, 0x6D 0x79 0x5F 0x74 0x65 0x73 0x74 0x2E, no +17, 0.00047375, STDIO, stdout, 0x63 0x3A 0x31 0x38 0x3A 0x74 0x65 0x73, no +18, 0.00048422, STDIO, stdout, 0x74 0x57 0x69 0x6C 0x6C 0x41 0x6C 0x77, no +19, 0.00049466, STDIO, stdout, 0x61 0x79 0x73 0x46 0x61 0x69 0x6C 0x3A, no +20, 0.00050543, STDIO, stdout, 0x46 0x41 0x49 0x4C 0x3A 0x20 0x45 0x78, no +21, 0.00051656, STDIO, stdout, 0x70 0x65 0x63 0x74 0x65 0x64 0x20 0x34, no +22, 0.00052931, STDIO, stdout, 0x32 0x20 0x57 0x61 0x73 0x20 0x31 0x74, no +23, 0.00053859, STDIO, stdout, 0x65 0x61 0x72 0x44 0x6F 0x77 0x6E 0x20, no +24, 0.00054788, STDIO, stdout, 0x6D 0x79 0x5F 0x74 0x65 0x73 0x74 0x0A, no +25, 0.00055255, STDIO, stdout, 0x0A 0x00 0x00 0x00 0x00 0x00 0x00 0x00, no +26, 0.00055673, STDIO, stdout, 0x0A 0x00 0x00 0x00 0x00 0x00 0x00 0x00, no +27, 0.00056722, STDIO, stdout, 0x2D 0x2D 0x2D 0x2D 0x2D 0x2D 0x2D 0x2D, no +28, 0.00057769, STDIO, stdout, 0x2D 0x2D 0x2D 0x2D 0x2D 0x2D 0x2D 0x2D, no +29, 0.00058813, STDIO, stdout, 0x2D 0x2D 0x2D 0x2D 0x2D 0x2D 0x2D 0x0A, no +30, 0.00059920, STDIO, stdout, 0x32 0x20 0x54 0x65 0x73 0x74 0x73 0x20, no +31, 0.00061042, STDIO, stdout, 0x31 0x20 0x46 0x61 0x69 0x6C 0x75 0x72, no +32, 0.00062156, STDIO, stdout, 0x65 0x73 0x20 0x30 0x20 0x49 0x67 0x6E, no +33, 0.00063024, STDIO, stdout, 0x6F 0x72 0x65 0x64 0x20 0x0A 0x00 0x00, no +34, 0.00063838, STDIO, stdout, 0x46 0x41 0x49 0x4C 0x0A 0x00 0x00 0x00, no diff --git a/MDK-ARM/EventRecorderStub.scvd b/MDK-ARM/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/MDK-ARM/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/MDK-ARM/RTE/Compiler/EventRecorderConf.h b/MDK-ARM/RTE/Compiler/EventRecorderConf.h new file mode 100644 index 0000000..bf3b1c0 --- /dev/null +++ b/MDK-ARM/RTE/Compiler/EventRecorderConf.h @@ -0,0 +1,34 @@ +/*------------------------------------------------------------------------------ + * MDK - Component ::Event Recorder + * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: EventRecorderConf.h + * Purpose: Event Recorder Configuration + * Rev.: V1.1.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 0 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines default time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/MDK-ARM/RTE/Device/STM32F103RB/RTE_Device.h b/MDK-ARM/RTE/Device/STM32F103RB/RTE_Device.h new file mode 100644 index 0000000..22d1da2 --- /dev/null +++ b/MDK-ARM/RTE/Device/STM32F103RB/RTE_Device.h @@ -0,0 +1,1828 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * $Date: 09. September 2016 + * $Revision: V1.1.2 + * + * Project: RTE Device Configuration for STMicroelectronics STM32F1xx + * + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 8000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 72000000 +// HCLK Clock <1-999999999> +#define RTE_HCLK 72000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 36000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 72000000 +// ADC Clock <1-999999999> +#define RTE_ADCCLK 36000000 +// USB Clock +#define RTE_USBCLK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 +#define RTE_USART1_TX_PORT_ID_DEF 0 +#if (RTE_USART1_TX_PORT_ID_DEF == 0) +#define RTE_USART1_TX_DEF 0 +#elif (RTE_USART1_TX_PORT_ID_DEF == 1) +#define RTE_USART1_TX_DEF 1 +#define RTE_USART1_TX_PORT_DEF GPIOA +#define RTE_USART1_TX_BIT_DEF 9 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 +#define RTE_USART1_RX_PORT_ID_DEF 0 +#if (RTE_USART1_RX_PORT_ID_DEF == 0) +#define RTE_USART1_RX_DEF 0 +#elif (RTE_USART1_RX_PORT_ID_DEF == 1) +#define RTE_USART1_RX_DEF 1 +#define RTE_USART1_RX_PORT_DEF GPIOA +#define RTE_USART1_RX_BIT_DEF 10 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_PORT_ID_DEF 0 +#if (RTE_USART1_CK_PORT_ID_DEF == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_PORT_ID_DEF == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT_DEF GPIOA +#define RTE_USART1_CK_BIT_DEF 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_PORT_ID_DEF 0 +#if (RTE_USART1_CTS_PORT_ID_DEF == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_PORT_ID_DEF == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT_DEF GPIOA +#define RTE_USART1_CTS_BIT_DEF 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_PORT_ID_DEF 0 +#if (RTE_USART1_RTS_PORT_ID_DEF == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_PORT_ID_DEF == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT_DEF GPIOA +#define RTE_USART1_RTS_BIT_DEF 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// USART1 Pin Remap +// Enable USART1 Pin Remapping +#define RTE_USART1_REMAP_FULL 0 + +// USART1_TX Pin <0=>Not Used <1=>PB6 +#define RTE_USART1_TX_PORT_ID_FULL 0 +#if (RTE_USART1_TX_PORT_ID_FULL == 0) +#define RTE_USART1_TX_FULL 0 +#elif (RTE_USART1_TX_PORT_ID_FULL == 1) +#define RTE_USART1_TX_FULL 1 +#define RTE_USART1_TX_PORT_FULL GPIOB +#define RTE_USART1_TX_BIT_FULL 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PB7 +#define RTE_USART1_RX_PORT_ID_FULL 0 +#if (RTE_USART1_RX_PORT_ID_FULL == 0) +#define RTE_USART1_RX_FULL 0 +#elif (RTE_USART1_RX_PORT_ID_FULL == 1) +#define RTE_USART1_RX_FULL 1 +#define RTE_USART1_RX_PORT_FULL GPIOB +#define RTE_USART1_RX_BIT_FULL 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif +// + +#if (RTE_USART1_REMAP_FULL) +#define RTE_USART1_AF_REMAP AFIO_USART1_REMAP +#define RTE_USART1_TX RTE_USART1_TX_FULL +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL +#define RTE_USART1_RX RTE_USART1_RX_FULL +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#else +#define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP +#define RTE_USART1_TX RTE_USART1_TX_DEF +#define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF +#define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF +#define RTE_USART1_RX RTE_USART1_RX_DEF +#define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF +#define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF +#define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF +#define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF +#define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF +#define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF +#define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF +#define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 1 +#define RTE_USART1_RX_DMA_CHANNEL 5 +#define RTE_USART1_RX_DMA_PRIORITY 0 +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 1 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 +#define RTE_USART2_TX_PORT_ID_DEF 0 +#if (RTE_USART2_TX_PORT_ID_DEF == 0) +#define RTE_USART2_TX_DEF 0 +#elif (RTE_USART2_TX_PORT_ID_DEF == 1) +#define RTE_USART2_TX_DEF 1 +#define RTE_USART2_TX_PORT_DEF GPIOA +#define RTE_USART2_TX_BIT_DEF 2 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 +#define RTE_USART2_RX_PORT_ID_DEF 0 +#if (RTE_USART2_RX_PORT_ID_DEF == 0) +#define RTE_USART2_RX_DEF 0 +#elif (RTE_USART2_RX_PORT_ID_DEF == 1) +#define RTE_USART2_RX_DEF 1 +#define RTE_USART2_RX_PORT_DEF GPIOA +#define RTE_USART2_RX_BIT_DEF 3 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 +#define RTE_USART2_CK_PORT_ID_DEF 0 +#if (RTE_USART2_CK_PORT_ID_DEF == 0) +#define RTE_USART2_CK_DEF 0 +#elif (RTE_USART2_CK_PORT_ID_DEF == 1) +#define RTE_USART2_CK_DEF 1 +#define RTE_USART2_CK_PORT_DEF GPIOA +#define RTE_USART2_CK_BIT_DEF 4 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 +#define RTE_USART2_CTS_PORT_ID_DEF 0 +#if (RTE_USART2_CTS_PORT_ID_DEF == 0) +#define RTE_USART2_CTS_DEF 0 +#elif (RTE_USART2_CTS_PORT_ID_DEF == 1) +#define RTE_USART2_CTS_DEF 1 +#define RTE_USART2_CTS_PORT_DEF GPIOA +#define RTE_USART2_CTS_BIT_DEF 0 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 +#define RTE_USART2_RTS_PORT_ID_DEF 0 +#if (RTE_USART2_RTS_PORT_ID_DEF == 0) +#define RTE_USART2_RTS_DEF 0 +#elif (RTE_USART2_RTS_PORT_ID_DEF == 1) +#define RTE_USART2_RTS_DEF 1 +#define RTE_USART2_RTS_PORT_DEF GPIOA +#define RTE_USART2_RTS_BIT_DEF 1 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// USART2 Pin Remap +// Enable USART2 Pin Remapping +#define RTE_USART2_REMAP_FULL 0 + +// USART2_TX Pin <0=>Not Used <1=>PD5 +#define RTE_USART2_TX_PORT_ID_FULL 0 +#if (RTE_USART2_TX_PORT_ID_FULL == 0) +#define RTE_USART2_TX_FULL 0 +#elif (RTE_USART2_TX_PORT_ID_FULL == 1) +#define RTE_USART2_TX_FULL 1 +#define RTE_USART2_TX_PORT_FULL GPIOD +#define RTE_USART2_TX_BIT_FULL 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PD6 +#define RTE_USART2_RX_PORT_ID_FULL 0 +#if (RTE_USART2_RX_PORT_ID_FULL == 0) +#define RTE_USART2_RX_FULL 0 +#elif (RTE_USART2_RX_PORT_ID_FULL == 1) +#define RTE_USART2_RX_FULL 1 +#define RTE_USART2_RX_PORT_FULL GPIOD +#define RTE_USART2_RX_BIT_FULL 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PD7 +#define RTE_USART2_CK_PORT_ID_FULL 0 +#if (RTE_USART2_CK_PORT_ID_FULL == 0) +#define RTE_USART2_CK_FULL 0 +#elif (RTE_USART2_CK_PORT_ID_FULL == 1) +#define RTE_USART2_CK_FULL 1 +#define RTE_USART2_CK_PORT_FULL GPIOD +#define RTE_USART2_CK_BIT_FULL 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PD3 +#define RTE_USART2_CTS_PORT_ID_FULL 0 +#if (RTE_USART2_CTS_PORT_ID_FULL == 0) +#define RTE_USART2_CTS_FULL 0 +#elif (RTE_USART2_CTS_PORT_ID_FULL == 1) +#define RTE_USART2_CTS_FULL 1 +#define RTE_USART2_CTS_PORT_FULL GPIOD +#define RTE_USART2_CTS_BIT_FULL 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PD4 +#define RTE_USART2_RTS_PORT_ID_FULL 0 +#if (RTE_USART2_RTS_PORT_ID_FULL == 0) +#define RTE_USART2_RTS_FULL 0 +#elif (RTE_USART2_RTS_PORT_ID_FULL == 1) +#define RTE_USART2_RTS_FULL 1 +#define RTE_USART2_RTS_PORT_FULL GPIOD +#define RTE_USART2_RTS_BIT_FULL 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif +// + +#if (RTE_USART2_REMAP_FULL) +#define RTE_USART2_AF_REMAP AFIO_USART2_REMAP +#define RTE_USART2_TX RTE_USART2_TX_FULL +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL +#define RTE_USART2_RX RTE_USART2_RX_FULL +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL +#define RTE_USART2_CK RTE_USART2_CK_FULL +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL +#define RTE_USART2_CTS RTE_USART2_CTS_FULL +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL +#define RTE_USART2_RTS RTE_USART2_RTS_FULL +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL +#else +#define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP +#define RTE_USART2_TX RTE_USART2_TX_DEF +#define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF +#define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF +#define RTE_USART2_RX RTE_USART2_RX_DEF +#define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF +#define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF +#define RTE_USART2_CK RTE_USART2_CK_DEF +#define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF +#define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF +#define RTE_USART2_CTS RTE_USART2_CTS_DEF +#define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF +#define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF +#define RTE_USART2_RTS RTE_USART2_RTS_DEF +#define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF +#define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_CHANNEL 6 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Set DMA Channel priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_CHANNEL 7 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 +#define RTE_USART3_TX_PORT_ID_DEF 0 +#if (RTE_USART3_TX_PORT_ID_DEF == 0) +#define RTE_USART3_TX_DEF 0 +#elif (RTE_USART3_TX_PORT_ID_DEF == 1) +#define RTE_USART3_TX_DEF 1 +#define RTE_USART3_TX_PORT_DEF GPIOB +#define RTE_USART3_TX_BIT_DEF 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 +#define RTE_USART3_RX_PORT_ID_DEF 0 +#if (RTE_USART3_RX_PORT_ID_DEF == 0) +#define RTE_USART3_RX_DEF 0 +#elif (RTE_USART3_RX_PORT_ID_DEF == 1) +#define RTE_USART3_RX_DEF 1 +#define RTE_USART3_RX_PORT_DEF GPIOB +#define RTE_USART3_RX_BIT_DEF 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 +#define RTE_USART3_CK_PORT_ID_DEF 0 +#if (RTE_USART3_CK_PORT_ID_DEF == 0) +#define RTE_USART3_CK_DEF 0 +#elif (RTE_USART3_CK_PORT_ID_DEF == 1) +#define RTE_USART3_CK_DEF 1 +#define RTE_USART3_CK_PORT_DEF GPIOB +#define RTE_USART3_CK_BIT_DEF 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 +#define RTE_USART3_CTS_PORT_ID_DEF 0 +#if (RTE_USART3_CTS_PORT_ID_DEF == 0) +#define RTE_USART3_CTS_DEF 0 +#elif (RTE_USART3_CTS_PORT_ID_DEF == 1) +#define RTE_USART3_CTS_DEF 1 +#define RTE_USART3_CTS_PORT_DEF GPIOB +#define RTE_USART3_CTS_BIT_DEF 13 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 +#define RTE_USART3_RTS_PORT_ID_DEF 0 +#if (RTE_USART3_RTS_PORT_ID_DEF == 0) +#define RTE_USART3_RTS_DEF 0 +#elif (RTE_USART3_RTS_PORT_ID_DEF == 1) +#define RTE_USART3_RTS_DEF 1 +#define RTE_USART3_RTS_PORT_DEF GPIOB +#define RTE_USART3_RTS_BIT_DEF 14 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// USART3 Partial Pin Remap +// Enable USART3 Partial Pin Remapping +#define RTE_USART3_REMAP_PARTIAL 0 + +// USART3_TX Pin <0=>Not Used <1=>PC10 +#define RTE_USART3_TX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_TX_PARTIAL 0 +#elif (RTE_USART3_TX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_TX_PARTIAL 1 +#define RTE_USART3_TX_PORT_PARTIAL GPIOC +#define RTE_USART3_TX_BIT_PARTIAL 10 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PC11 +#define RTE_USART3_RX_PORT_ID_PARTIAL 0 +#if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) +#define RTE_USART3_RX_PARTIAL 0 +#elif (RTE_USART3_RX_PORT_ID_PARTIAL == 1) +#define RTE_USART3_RX_PARTIAL 1 +#define RTE_USART3_RX_PORT_PARTIAL GPIOC +#define RTE_USART3_RX_BIT_PARTIAL 11 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PC12 +#define RTE_USART3_CK_PORT_ID_PARTIAL 0 +#if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) +#define RTE_USART3_CK_PARTIAL 0 +#elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) +#define RTE_USART3_CK_PARTIAL 1 +#define RTE_USART3_CK_PORT_PARTIAL GPIOC +#define RTE_USART3_CK_BIT_PARTIAL 12 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif +// + +// USART3 Full Pin Remap +// Enable USART3 Full Pin Remapping +#define RTE_USART3_REMAP_FULL 0 + +// USART3_TX Pin <0=>Not Used <1=>PD8 +#define RTE_USART3_TX_PORT_ID_FULL 0 +#if (RTE_USART3_TX_PORT_ID_FULL == 0) +#define RTE_USART3_TX_FULL 0 +#elif (RTE_USART3_TX_PORT_ID_FULL == 1) +#define RTE_USART3_TX_FULL 1 +#define RTE_USART3_TX_PORT_FULL GPIOD +#define RTE_USART3_TX_BIT_FULL 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PD9 +#define RTE_USART3_RX_PORT_ID_FULL 0 +#if (RTE_USART3_RX_PORT_ID_FULL == 0) +#define RTE_USART3_RX_FULL 0 +#elif (RTE_USART3_RX_PORT_ID_FULL == 1) +#define RTE_USART3_RX_FULL 1 +#define RTE_USART3_RX_PORT_FULL GPIOD +#define RTE_USART3_RX_BIT_FULL 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PD10 +#define RTE_USART3_CK_PORT_ID_FULL 0 +#if (RTE_USART3_CK_PORT_ID_FULL == 0) +#define RTE_USART3_CK_FULL 0 +#elif (RTE_USART3_CK_PORT_ID_FULL == 1) +#define RTE_USART3_CK_FULL 1 +#define RTE_USART3_CK_PORT_FULL GPIOD +#define RTE_USART3_CK_BIT_FULL 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PD11 +#define RTE_USART3_CTS_PORT_ID_FULL 0 +#if (RTE_USART3_CTS_PORT_ID_FULL == 0) +#define RTE_USART3_CTS_FULL 0 +#elif (RTE_USART3_CTS_PORT_ID_FULL == 1) +#define RTE_USART3_CTS_FULL 1 +#define RTE_USART3_CTS_PORT_FULL GPIOD +#define RTE_USART3_CTS_BIT_FULL 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PD12 +#define RTE_USART3_RTS_PORT_ID_FULL 0 +#if (RTE_USART3_RTS_PORT_ID_FULL == 0) +#define RTE_USART3_RTS_FULL 0 +#elif (RTE_USART3_RTS_PORT_ID_FULL == 1) +#define RTE_USART3_RTS_FULL 1 +#define RTE_USART3_RTS_PORT_FULL GPIOD +#define RTE_USART3_RTS_BIT_FULL 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif +// + +#if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) +#error "Invalid USART3 Pin Remap Configuration!" +#endif + +#if (RTE_USART3_REMAP_FULL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL +#define RTE_USART3_TX RTE_USART3_TX_FULL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL +#define RTE_USART3_RX RTE_USART3_RX_FULL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL +#define RTE_USART3_CK RTE_USART3_CK_FULL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL +#define RTE_USART3_CTS RTE_USART3_CTS_FULL +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL +#define RTE_USART3_RTS RTE_USART3_RTS_FULL +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL +#elif (RTE_USART3_REMAP_PARTIAL) +#define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL +#define RTE_USART3_TX RTE_USART3_TX_PARTIAL +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL +#define RTE_USART3_RX RTE_USART3_RX_PARTIAL +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL +#define RTE_USART3_CK RTE_USART3_CK_PARTIAL +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#else +#define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP +#define RTE_USART3_TX RTE_USART3_TX_DEF +#define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF +#define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF +#define RTE_USART3_RX RTE_USART3_RX_DEF +#define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF +#define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF +#define RTE_USART3_CK RTE_USART3_CK_DEF +#define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF +#define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF +#define RTE_USART3_CTS RTE_USART3_CTS_DEF +#define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF +#define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF +#define RTE_USART3_RTS RTE_USART3_RTS_DEF +#define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF +#define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_CHANNEL 3 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_CHANNEL 2 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 +#define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART4_TX Pin <0=>Not Used <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 2 +#define RTE_UART4_RX_DMA_CHANNEL 3 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very high +// Sets DMA Channel priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 2 +#define RTE_UART4_TX_DMA_CHANNEL 5 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 +#define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// UART5_TX Pin <0=>Not Used <1=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif +// + + +// I2C1 (Inter-integrated Circuit Interface 1) +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 +#define RTE_I2C1_SCL_PORT_ID_DEF 0 +#if (RTE_I2C1_SCL_PORT_ID_DEF == 0) +#define RTE_I2C1_SCL_PORT_DEF GPIOB +#define RTE_I2C1_SCL_BIT_DEF 6 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 +#define RTE_I2C1_SDA_PORT_ID_DEF 0 +#if (RTE_I2C1_SDA_PORT_ID_DEF == 0) +#define RTE_I2C1_SDA_PORT_DEF GPIOB +#define RTE_I2C1_SDA_BIT_DEF 7 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1 Pin Remap +// Enable I2C1 Pin Remapping +#define RTE_I2C1_REMAP_FULL 0 + +// I2C1_SCL Pin <0=>PB8 +#define RTE_I2C1_SCL_PORT_ID_FULL 0 +#if (RTE_I2C1_SCL_PORT_ID_FULL == 0) +#define RTE_I2C1_SCL_PORT_FULL GPIOB +#define RTE_I2C1_SCL_BIT_FULL 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB9 +#define RTE_I2C1_SDA_PORT_ID_FULL 0 +#if (RTE_I2C1_SDA_PORT_ID_FULL == 0) +#define RTE_I2C1_SDA_PORT_FULL GPIOB +#define RTE_I2C1_SDA_BIT_FULL 9 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// + +#if (RTE_I2C1_REMAP_FULL) +#define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL +#else +#define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP +#define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF +#define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF +#define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF +#define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF +#endif + + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_CHANNEL 7 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <6=>6 +// Selects DMA Channel (only Channel 6 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_CHANNEL 6 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 +#define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP + +// I2C2_SCL Pin <0=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_CHANNEL 5 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_CHANNEL 4 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 +#define RTE_SPI1_SCK_PORT_ID_DEF 0 +#if (RTE_SPI1_SCK_PORT_ID_DEF == 0) +#define RTE_SPI1_SCK_PORT_DEF GPIOA +#define RTE_SPI1_SCK_BIT_DEF 5 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 +#define RTE_SPI1_MISO_PORT_ID_DEF 0 +#if (RTE_SPI1_MISO_PORT_ID_DEF == 0) +#define RTE_SPI1_MISO_DEF 0 +#elif (RTE_SPI1_MISO_PORT_ID_DEF == 1) +#define RTE_SPI1_MISO_DEF 1 +#define RTE_SPI1_MISO_PORT_DEF GPIOA +#define RTE_SPI1_MISO_BIT_DEF 6 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 +#define RTE_SPI1_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI1_MOSI_DEF 0 +#elif (RTE_SPI1_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI1_MOSI_DEF 1 +#define RTE_SPI1_MOSI_PORT_DEF GPIOA +#define RTE_SPI1_MOSI_BIT_DEF 7 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1 Pin Remap +// Enable SPI1 Pin Remapping. +#define RTE_SPI1_REMAP 0 + +// SPI1_SCK Pin <0=>PB3 +#define RTE_SPI1_SCK_PORT_ID_FULL 0 +#if (RTE_SPI1_SCK_PORT_ID_FULL == 0) +#define RTE_SPI1_SCK_PORT_FULL GPIOB +#define RTE_SPI1_SCK_BIT_FULL 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID_FULL 0 +#if (RTE_SPI1_MISO_PORT_ID_FULL == 0) +#define RTE_SPI1_MISO_FULL 0 +#elif (RTE_SPI1_MISO_PORT_ID_FULL == 1) +#define RTE_SPI1_MISO_FULL 1 +#define RTE_SPI1_MISO_PORT_FULL GPIOB +#define RTE_SPI1_MISO_BIT_FULL 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif +// SPI1_MOSI Pin <0=>Not Used <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI1_MOSI_FULL 0 +#elif (RTE_SPI1_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI1_MOSI_FULL 1 +#define RTE_SPI1_MOSI_PORT_FULL GPIOB +#define RTE_SPI1_MOSI_BIT_FULL 5 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI1_REMAP) +#define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL +#define RTE_SPI1_MISO RTE_SPI1_MISO_FULL +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_FULL +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL +#else +#define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP +#define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF +#define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF +#define RTE_SPI1_MISO RTE_SPI1_MISO_DEF +#define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF +#define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF +#define RTE_SPI1_MOSI RTE_SPI1_MOSI_DEF +#define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF +#define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 1 +#define RTE_SPI1_RX_DMA_CHANNEL 2 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 1 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB13 +#define RTE_SPI2_SCK_PORT_ID 0 +#if (RTE_SPI2_SCK_PORT_ID == 0) +#define RTE_SPI2_SCK_PORT GPIOB +#define RTE_SPI2_SCK_BIT 13 +#define RTE_SPI2_SCK_REMAP 0 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#define RTE_SPI2_MISO_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#define RTE_SPI2_MOSI_REMAP 0 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_CHANNEL 4 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_CHANNEL 5 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..G, y = 0..15) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 +#define RTE_SPI3_SCK_PORT_ID_DEF 0 +#if (RTE_SPI3_SCK_PORT_ID_DEF == 0) +#define RTE_SPI3_SCK_PORT_DEF GPIOB +#define RTE_SPI3_SCK_BIT_DEF 3 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 +#define RTE_SPI3_MISO_PORT_ID_DEF 0 +#if (RTE_SPI3_MISO_PORT_ID_DEF == 0) +#define RTE_SPI3_MISO_DEF 0 +#elif (RTE_SPI3_MISO_PORT_ID_DEF == 1) +#define RTE_SPI3_MISO_DEF 1 +#define RTE_SPI3_MISO_PORT_DEF GPIOB +#define RTE_SPI3_MISO_BIT_DEF 4 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI <0=>Not Used Pin <1=>PB5 +#define RTE_SPI3_MOSI_PORT_ID_DEF 0 +#if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) +#define RTE_SPI3_MOSI_DEF 0 +#elif (RTE_SPI3_MOSI_PORT_ID_DEF == 1) +#define RTE_SPI3_MOSI_DEF 1 +#define RTE_SPI3_MOSI_PORT_DEF GPIOB +#define RTE_SPI3_MOSI_BIT_DEF 5 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3 Pin Remap +// Enable SPI3 Pin Remapping. +// SPI 3 Pin Remapping is available only in connectivity line devices! +#define RTE_SPI3_REMAP 0 + +// SPI3_SCK Pin <0=>PC10 +#define RTE_SPI3_SCK_PORT_ID_FULL 0 +#if (RTE_SPI3_SCK_PORT_ID_FULL == 0) +#define RTE_SPI3_SCK_PORT_FULL GPIOC +#define RTE_SPI3_SCK_BIT_FULL 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>Not Used <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID_FULL 0 +#if (RTE_SPI3_MISO_PORT_ID_FULL == 0) +#define RTE_SPI3_MISO_FULL 0 +#elif (RTE_SPI3_MISO_PORT_ID_FULL == 1) +#define RTE_SPI3_MISO_FULL 1 +#define RTE_SPI3_MISO_PORT_FULL GPIOC +#define RTE_SPI3_MISO_BIT_FULL 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif +// SPI3_MOSI Pin <0=>Not Used <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID_FULL 0 +#if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) +#define RTE_SPI3_MOSI_FULL 0 +#elif (RTE_SPI3_MOSI_PORT_ID_FULL == 1) +#define RTE_SPI3_MOSI_FULL 1 +#define RTE_SPI3_MOSI_PORT_FULL GPIOC +#define RTE_SPI3_MOSI_BIT_FULL 12 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// + +#if (RTE_SPI3_REMAP) +#define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL +#define RTE_SPI3_MISO RTE_SPI3_MISO_FULL +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_FULL +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL +#else +#define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP +#define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF +#define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF +#define RTE_SPI3_MISO RTE_SPI3_MISO_DEF +#define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF +#define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF +#define RTE_SPI3_MOSI RTE_SPI3_MOSI_DEF +#define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF +#define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 2 +#define RTE_SPI3_RX_DMA_CHANNEL 1 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 2 +#define RTE_SPI3_TX_DMA_CHANNEL 2 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDIO 0 + +// SDIO Peripheral Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) + #define RTE_SDIO_CK_PORT GPIOC + #define RTE_SDIO_CK_PIN 12 +#else + #error "Invalid SDIO_CLK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) + #define RTE_SDIO_CMD_PORT GPIOD + #define RTE_SDIO_CMD_PIN 2 +#else + #error "Invalid SDIO_CMD Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) + #define RTE_SDIO_D0_PORT GPIOC + #define RTE_SDIO_D0_PIN 8 +#else + #error "Invalid SDIO_DAT0 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +#define RTE_SDIO_BUS_WIDTH_4 1 +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) + #define RTE_SDIO_D1_PORT GPIOC + #define RTE_SDIO_D1_PIN 9 +#else + #error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) + #define RTE_SDIO_D2_PORT GPIOC + #define RTE_SDIO_D2_PIN 10 +#else + #error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) + #define RTE_SDIO_D3_PORT GPIOC + #define RTE_SDIO_D3_PIN 11 +#else + #error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D[1 .. 3] +// SDIO_D[4 .. 7] +#define RTE_SDIO_BUS_WIDTH_8 0 +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) + #define RTE_SDIO_D4_PORT GPIOB + #define RTE_SDIO_D4_PIN 8 +#else + #error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) + #define RTE_SDIO_D5_PORT GPIOB + #define RTE_SDIO_D5_PIN 9 +#else + #error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) + #define RTE_SDIO_D6_PORT GPIOC + #define RTE_SDIO_D6_PIN 6 +#else + #error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) + #define RTE_SDIO_D7_PORT GPIOC + #define RTE_SDIO_D7_PIN 7 +#else + #error "Invalid SDIO_D7 Pin Configuration!" +#endif +// SDIO_D[4 .. 7] +// SDIO Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_EN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(5) +#define RTE_SDIO_CD_PIN 11 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_EN 0 +#define RTE_SDIO_WP_ACTIVE 1 +#define RTE_SDIO_WP_PORT GPIO_PORT(0) +#define RTE_SDIO_WP_PIN 10 + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT 11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT 8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT 0 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT 12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT 9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT 1 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT 12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT 13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +// Enable Media Independent Interface pin configuration +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_DEF 0 + +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_DEF 0 + +// ETH_MII_RXD2 Pin <0=>PB0 +#define RTE_ETH_MII_RXD2_DEF 0 + +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 +#define RTE_ETH_MII_RXD3_DEF 0 + +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_DEF 0 + +// ETH_MII_RX_ER Pin <0=>PB10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_MII_REMAP 0 + +// ETH_MII_RXD0 Pin <1=>PD9 +#define RTE_ETH_MII_RXD0_REMAP 1 + +// ETH_MII_RXD1 Pin <1=>PD10 +#define RTE_ETH_MII_RXD1_REMAP 1 + +// ETH_MII_RXD2 Pin <1=>PD11 +#define RTE_ETH_MII_RXD2_REMAP 1 + +// ETH_MII_RXD3 Pin <1=>PD12 +#define RTE_ETH_MII_RXD3_REMAP 1 + +// ETH_MII_RX_DV Pin <1=>PD8 +#define RTE_ETH_MII_RX_DV_REMAP 1 +// + +// + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) +#define RTE_ETH_MII_RXD0_PORT GPIOD +#define RTE_ETH_MII_RXD0_PIN 9 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) +#define RTE_ETH_MII_RXD1_PORT GPIOD +#define RTE_ETH_MII_RXD1_PIN 10 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) +#define RTE_ETH_MII_RXD2_PORT GPIOD +#define RTE_ETH_MII_RXD2_PIN 11 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) +#define RTE_ETH_MII_RXD3_PORT GPIOD +#define RTE_ETH_MII_RXD3_PIN 12 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif + +#if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) +#define RTE_ETH_MII_RX_DV_PORT GPIOD +#define RTE_ETH_MII_RX_DV_PIN 8 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_DEF 0 + +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_DEF 0 + +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_DEF 0 + +// Ethernet MAC I/O remapping +// Remap Ethernet pins +#define RTE_ETH_RMII_REMAP 0 +// ETH_RMII_RXD0 Pin <1=>PD9 +#define RTE_ETH_RMII_RXD0_REMAP 1 + +// ETH_RMII_RXD1 Pin <1=>PD10 +#define RTE_ETH_RMII_RXD1_REMAP 1 + +// ETH_RMII_CRS_DV Pin <1=>PD8 +#define RTE_ETH_RMII_CRS_DV_REMAP 1 +// + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) +#define RTE_ETH_RMII_RXD0_PORT GPIOD +#define RTE_ETH_RMII_RXD0_PIN 9 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) +#define RTE_ETH_RMII_RXD1_PORT GPIOD +#define RTE_ETH_RMII_RXD1_PIN 10 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif + +#if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOD +#define RTE_ETH_RMII_CRS_DV_PIN 8 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled +#define RTE_ETH_REF_CLOCK_ID 0 +#if (RTE_ETH_REF_CLOCK_ID == 0) +#define RTE_ETH_REF_CLOCK 0 +#elif (RTE_ETH_REF_CLOCK_ID == 1) +#define RTE_ETH_REF_CLOCK 1 +#else +#error "Invalid MCO Ethernet Reference Clock Configuration!" +#endif +// + + +// USB Device Full-speed +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_DEVICE 0 + +// CON On/Off Pin +// Configure Pin for driving D+ pull-up +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_USB_DEVICE_CON_PIN 1 +#define RTE_USB_DEVICE_CON_ACTIVE 0 +#define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) +#define RTE_USB_DEVICE_CON_BIT 14 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_FS_VBUS_BIT 9 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..G, y = 0..15) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(4) +#define RTE_OTG_FS_OC_BIT 1 +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/MDK-ARM/RTE/Device/STM32F103RB/startup_stm32f10x_md.s b/MDK-ARM/RTE/Device/STM32F103RB/startup_stm32f10x_md.s new file mode 100644 index 0000000..74da96c --- /dev/null +++ b/MDK-ARM/RTE/Device/STM32F103RB/startup_stm32f10x_md.s @@ -0,0 +1,307 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f10x_md.s +;* Author : MCD Application Team +;* Version : V3.5.0 +;* Date : 11-March-2011 +;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM +;* toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Configure the clock system +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD TAMPER_IRQHandler ; Tamper + DCD RTC_IRQHandler ; RTC + DCD FLASH_IRQHandler ; Flash + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line 0 + DCD EXTI1_IRQHandler ; EXTI Line 1 + DCD EXTI2_IRQHandler ; EXTI Line 2 + DCD EXTI3_IRQHandler ; EXTI Line 3 + DCD EXTI4_IRQHandler ; EXTI Line 4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1_2 + DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX + DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 + DCD TIM1_BRK_IRQHandler ; TIM1 Break + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 + DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMPER_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] + EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTCAlarm_IRQHandler [WEAK] + EXPORT USBWakeUp_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMPER_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +USB_HP_CAN1_TX_IRQHandler +USB_LP_CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTCAlarm_IRQHandler +USBWakeUp_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/MDK-ARM/RTE/Device/STM32F103RB/system_stm32f10x.c b/MDK-ARM/RTE/Device/STM32F103RB/system_stm32f10x.c new file mode 100644 index 0000000..71efc85 --- /dev/null +++ b/MDK-ARM/RTE/Device/STM32F103RB/system_stm32f10x.c @@ -0,0 +1,1094 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_VALUE <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/MDK-ARM/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s b/MDK-ARM/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s new file mode 100644 index 0000000..6ba6ac7 --- /dev/null +++ b/MDK-ARM/RTE/Device/STM32F429ZITx/startup_stm32f429xx.s @@ -0,0 +1,463 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f429xx.s +;* Author : MCD Application Team +;* Description : STM32F429x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/MDK-ARM/RTE/Device/STM32F429ZITx/system_stm32f4xx.c b/MDK-ARM/RTE/Device/STM32F429ZITx/system_stm32f4xx.c new file mode 100644 index 0000000..3303f96 --- /dev/null +++ b/MDK-ARM/RTE/Device/STM32F429ZITx/system_stm32f4xx.c @@ -0,0 +1,761 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/MDK-ARM/RTE/RTE_Components.h b/MDK-ARM/RTE/RTE_Components.h deleted file mode 100644 index 8441218..0000000 --- a/MDK-ARM/RTE/RTE_Components.h +++ /dev/null @@ -1,20 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'stm32-keil-unity' - * Target: 'STM32F429I' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "stm32f4xx.h" - - -#endif /* RTE_COMPONENTS_H */ diff --git a/MDK-ARM/RTE/_Test/RTE_Components.h b/MDK-ARM/RTE/_Test/RTE_Components.h new file mode 100644 index 0000000..30e42e2 --- /dev/null +++ b/MDK-ARM/RTE/_Test/RTE_Components.h @@ -0,0 +1,27 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'stm32-keil-unity' + * Target: 'Test' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f10x.h" + +/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.4.0 */ +#define RTE_Compiler_EventRecorder + #define RTE_Compiler_EventRecorder_DAP +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:EVR:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/MDK-ARM/simulator.ini b/MDK-ARM/simulator.ini index 6f7cac0..61e9935 100644 --- a/MDK-ARM/simulator.ini +++ b/MDK-ARM/simulator.ini @@ -1,4 +1,10 @@ -MAP 0x40000000, 0x400FFFFF READ WRITE - -ITMLOG 0 > ..\Log\ITM0.log +MAP 0xE0001000, 0xE0001007 READ WRITE +signal void DWT_CYCCNT (void) { + while (1) { + rwatch(0xE0001004); + _WWORD(0xE0001004, states); + } +} +DWT_CYCCNT() +ER >..\Log\ITM0.log \ No newline at end of file diff --git a/MDK-ARM/startup_stm32f10x_md.lst b/MDK-ARM/startup_stm32f10x_md.lst new file mode 100644 index 0000000..20458f6 --- /dev/null +++ b/MDK-ARM/startup_stm32f10x_md.lst @@ -0,0 +1,1181 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2011 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f10x_md.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Version : V3.5.0 + 5 00000000 ;* Date : 11-March-2011 + 6 00000000 ;* Description : STM32F10x Medium Density Devices + vector table for MDK-ARM + 7 00000000 ;* toolchain. + 8 00000000 ;* This module performs: + 9 00000000 ;* - Set the initial SP + 10 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 11 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 12 00000000 ;* - Configure the clock system + 13 00000000 ;* - Branches to __main in the C li + brary (which eventually + 14 00000000 ;* calls main()). + 15 00000000 ;* After Reset the CortexM3 process + or is in Thread mode, + 16 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 17 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 18 00000000 ;******************************************************* + ************************ + 19 00000000 ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS A + T PROVIDING CUSTOMERS + 20 00000000 ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN OR + DER FOR THEM TO SAVE TIME. + 21 00000000 ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIAB + LE FOR ANY DIRECT, + 22 00000000 ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY + CLAIMS ARISING FROM THE + 23 00000000 ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOM + ERS OF THE CODING + 24 00000000 ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR + PRODUCTS. + 25 00000000 ;******************************************************* + ************************ + 26 00000000 + 27 00000000 ; Amount of memory (in bytes) allocated for Stack + 28 00000000 ; Tailor this value to your application needs + 29 00000000 ; Stack Configuration + 30 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 31 00000000 ; + 32 00000000 + 33 00000000 00000400 + Stack_Size + EQU 0x00000400 + 34 00000000 + 35 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 36 00000000 Stack_Mem + SPACE Stack_Size + 37 00000400 __initial_sp + 38 00000400 + 39 00000400 + 40 00000400 ; Heap Configuration + + + +ARM Macro Assembler Page 2 + + + 41 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 42 00000400 ; + 43 00000400 + 44 00000400 00000200 + Heap_Size + EQU 0x00000200 + 45 00000400 + 46 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 47 00000000 __heap_base + 48 00000000 Heap_Mem + SPACE Heap_Size + 49 00000200 __heap_limit + 50 00000200 + 51 00000200 PRESERVE8 + 52 00000200 THUMB + 53 00000200 + 54 00000200 + 55 00000200 ; Vector Table Mapped to Address 0 at Reset + 56 00000200 AREA RESET, DATA, READONLY + 57 00000000 EXPORT __Vectors + 58 00000000 EXPORT __Vectors_End + 59 00000000 EXPORT __Vectors_Size + 60 00000000 + 61 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 62 00000004 00000000 DCD Reset_Handler ; Reset Handler + 63 00000008 00000000 DCD NMI_Handler ; NMI Handler + 64 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + 65 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 66 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 67 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 68 0000001C 00000000 DCD 0 ; Reserved + 69 00000020 00000000 DCD 0 ; Reserved + 70 00000024 00000000 DCD 0 ; Reserved + 71 00000028 00000000 DCD 0 ; Reserved + 72 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 73 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 74 00000034 00000000 DCD 0 ; Reserved + 75 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 76 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 77 00000040 + 78 00000040 ; External Interrupts + 79 00000040 00000000 DCD WWDG_IRQHandler + ; Window Watchdog + 80 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detect + 81 00000048 00000000 DCD TAMPER_IRQHandler ; Tamper + 82 0000004C 00000000 DCD RTC_IRQHandler ; RTC + + + +ARM Macro Assembler Page 3 + + + 83 00000050 00000000 DCD FLASH_IRQHandler ; Flash + 84 00000054 00000000 DCD RCC_IRQHandler ; RCC + 85 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line 0 + 86 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line 1 + 87 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line 2 + 88 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line 3 + 89 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line 4 + 90 0000006C 00000000 DCD DMA1_Channel1_IRQHandler + ; DMA1 Channel 1 + 91 00000070 00000000 DCD DMA1_Channel2_IRQHandler + ; DMA1 Channel 2 + 92 00000074 00000000 DCD DMA1_Channel3_IRQHandler + ; DMA1 Channel 3 + 93 00000078 00000000 DCD DMA1_Channel4_IRQHandler + ; DMA1 Channel 4 + 94 0000007C 00000000 DCD DMA1_Channel5_IRQHandler + ; DMA1 Channel 5 + 95 00000080 00000000 DCD DMA1_Channel6_IRQHandler + ; DMA1 Channel 6 + 96 00000084 00000000 DCD DMA1_Channel7_IRQHandler + ; DMA1 Channel 7 + 97 00000088 00000000 DCD ADC1_2_IRQHandler ; ADC1_2 + 98 0000008C 00000000 DCD USB_HP_CAN1_TX_IRQHandler ; USB + High Priority or C + AN1 TX + 99 00000090 00000000 DCD USB_LP_CAN1_RX0_IRQHandler ; US + B Low Priority or + CAN1 RX0 + 100 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + 101 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE + 102 0000009C 00000000 DCD EXTI9_5_IRQHandler + ; EXTI Line 9..5 + 103 000000A0 00000000 DCD TIM1_BRK_IRQHandler + ; TIM1 Break + 104 000000A4 00000000 DCD TIM1_UP_IRQHandler + ; TIM1 Update + 105 000000A8 00000000 DCD TIM1_TRG_COM_IRQHandler ; TIM1 + Trigger and Commuta + tion + 106 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + 107 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 + 108 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 + 109 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 + 110 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event + + 111 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error + + 112 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event + + 113 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error + + 114 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 + 115 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 + 116 000000D4 00000000 DCD USART1_IRQHandler ; USART1 + 117 000000D8 00000000 DCD USART2_IRQHandler ; USART2 + 118 000000DC 00000000 DCD USART3_IRQHandler ; USART3 + 119 000000E0 00000000 DCD EXTI15_10_IRQHandler + ; EXTI Line 15..10 + + + +ARM Macro Assembler Page 4 + + + 120 000000E4 00000000 DCD RTCAlarm_IRQHandler ; RTC Alarm + through EXTI Line + 121 000000E8 00000000 DCD USBWakeUp_IRQHandler ; USB Wake + up from suspend + 122 000000EC __Vectors_End + 123 000000EC + 124 000000EC 000000EC + __Vectors_Size + EQU __Vectors_End - __Vectors + 125 000000EC + 126 000000EC AREA |.text|, CODE, READONLY + 127 00000000 + 128 00000000 ; Reset handler + 129 00000000 Reset_Handler + PROC + 130 00000000 EXPORT Reset_Handler [WEAK +] + 131 00000000 IMPORT __main + 132 00000000 IMPORT SystemInit + 133 00000000 4806 LDR R0, =SystemInit + 134 00000002 4780 BLX R0 + 135 00000004 4806 LDR R0, =__main + 136 00000006 4700 BX R0 + 137 00000008 ENDP + 138 00000008 + 139 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 140 00000008 + 141 00000008 NMI_Handler + PROC + 142 00000008 EXPORT NMI_Handler [WEA +K] + 143 00000008 E7FE B . + 144 0000000A ENDP + 146 0000000A HardFault_Handler + PROC + 147 0000000A EXPORT HardFault_Handler [WEA +K] + 148 0000000A E7FE B . + 149 0000000C ENDP + 151 0000000C MemManage_Handler + PROC + 152 0000000C EXPORT MemManage_Handler [WEA +K] + 153 0000000C E7FE B . + 154 0000000E ENDP + 156 0000000E BusFault_Handler + PROC + 157 0000000E EXPORT BusFault_Handler [WEA +K] + 158 0000000E E7FE B . + 159 00000010 ENDP + 161 00000010 UsageFault_Handler + PROC + 162 00000010 EXPORT UsageFault_Handler [WEA +K] + 163 00000010 E7FE B . + 164 00000012 ENDP + 165 00000012 SVC_Handler + + + +ARM Macro Assembler Page 5 + + + PROC + 166 00000012 EXPORT SVC_Handler [WEA +K] + 167 00000012 E7FE B . + 168 00000014 ENDP + 170 00000014 DebugMon_Handler + PROC + 171 00000014 EXPORT DebugMon_Handler [WEA +K] + 172 00000014 E7FE B . + 173 00000016 ENDP + 174 00000016 PendSV_Handler + PROC + 175 00000016 EXPORT PendSV_Handler [WEA +K] + 176 00000016 E7FE B . + 177 00000018 ENDP + 178 00000018 SysTick_Handler + PROC + 179 00000018 EXPORT SysTick_Handler [WEA +K] + 180 00000018 E7FE B . + 181 0000001A ENDP + 182 0000001A + 183 0000001A Default_Handler + PROC + 184 0000001A + 185 0000001A EXPORT WWDG_IRQHandler [WEA +K] + 186 0000001A EXPORT PVD_IRQHandler [WEA +K] + 187 0000001A EXPORT TAMPER_IRQHandler [WEA +K] + 188 0000001A EXPORT RTC_IRQHandler [WEA +K] + 189 0000001A EXPORT FLASH_IRQHandler [WEA +K] + 190 0000001A EXPORT RCC_IRQHandler [WEA +K] + 191 0000001A EXPORT EXTI0_IRQHandler [WEA +K] + 192 0000001A EXPORT EXTI1_IRQHandler [WEA +K] + 193 0000001A EXPORT EXTI2_IRQHandler [WEA +K] + 194 0000001A EXPORT EXTI3_IRQHandler [WEA +K] + 195 0000001A EXPORT EXTI4_IRQHandler [WEA +K] + 196 0000001A EXPORT DMA1_Channel1_IRQHandler [WEA +K] + 197 0000001A EXPORT DMA1_Channel2_IRQHandler [WEA +K] + 198 0000001A EXPORT DMA1_Channel3_IRQHandler [WEA +K] + 199 0000001A EXPORT DMA1_Channel4_IRQHandler [WEA +K] + 200 0000001A EXPORT DMA1_Channel5_IRQHandler [WEA +K] + + + +ARM Macro Assembler Page 6 + + + 201 0000001A EXPORT DMA1_Channel6_IRQHandler [WEA +K] + 202 0000001A EXPORT DMA1_Channel7_IRQHandler [WEA +K] + 203 0000001A EXPORT ADC1_2_IRQHandler [WEA +K] + 204 0000001A EXPORT USB_HP_CAN1_TX_IRQHandler [WEA +K] + 205 0000001A EXPORT USB_LP_CAN1_RX0_IRQHandler [WEA +K] + 206 0000001A EXPORT CAN1_RX1_IRQHandler [WEA +K] + 207 0000001A EXPORT CAN1_SCE_IRQHandler [WEA +K] + 208 0000001A EXPORT EXTI9_5_IRQHandler [WEA +K] + 209 0000001A EXPORT TIM1_BRK_IRQHandler [WEA +K] + 210 0000001A EXPORT TIM1_UP_IRQHandler [WEA +K] + 211 0000001A EXPORT TIM1_TRG_COM_IRQHandler [WEA +K] + 212 0000001A EXPORT TIM1_CC_IRQHandler [WEA +K] + 213 0000001A EXPORT TIM2_IRQHandler [WEA +K] + 214 0000001A EXPORT TIM3_IRQHandler [WEA +K] + 215 0000001A EXPORT TIM4_IRQHandler [WEA +K] + 216 0000001A EXPORT I2C1_EV_IRQHandler [WEA +K] + 217 0000001A EXPORT I2C1_ER_IRQHandler [WEA +K] + 218 0000001A EXPORT I2C2_EV_IRQHandler [WEA +K] + 219 0000001A EXPORT I2C2_ER_IRQHandler [WEA +K] + 220 0000001A EXPORT SPI1_IRQHandler [WEA +K] + 221 0000001A EXPORT SPI2_IRQHandler [WEA +K] + 222 0000001A EXPORT USART1_IRQHandler [WEA +K] + 223 0000001A EXPORT USART2_IRQHandler [WEA +K] + 224 0000001A EXPORT USART3_IRQHandler [WEA +K] + 225 0000001A EXPORT EXTI15_10_IRQHandler [WEA +K] + 226 0000001A EXPORT RTCAlarm_IRQHandler [WEA +K] + 227 0000001A EXPORT USBWakeUp_IRQHandler [WEA +K] + 228 0000001A + 229 0000001A WWDG_IRQHandler + 230 0000001A PVD_IRQHandler + 231 0000001A TAMPER_IRQHandler + 232 0000001A RTC_IRQHandler + + + +ARM Macro Assembler Page 7 + + + 233 0000001A FLASH_IRQHandler + 234 0000001A RCC_IRQHandler + 235 0000001A EXTI0_IRQHandler + 236 0000001A EXTI1_IRQHandler + 237 0000001A EXTI2_IRQHandler + 238 0000001A EXTI3_IRQHandler + 239 0000001A EXTI4_IRQHandler + 240 0000001A DMA1_Channel1_IRQHandler + 241 0000001A DMA1_Channel2_IRQHandler + 242 0000001A DMA1_Channel3_IRQHandler + 243 0000001A DMA1_Channel4_IRQHandler + 244 0000001A DMA1_Channel5_IRQHandler + 245 0000001A DMA1_Channel6_IRQHandler + 246 0000001A DMA1_Channel7_IRQHandler + 247 0000001A ADC1_2_IRQHandler + 248 0000001A USB_HP_CAN1_TX_IRQHandler + 249 0000001A USB_LP_CAN1_RX0_IRQHandler + 250 0000001A CAN1_RX1_IRQHandler + 251 0000001A CAN1_SCE_IRQHandler + 252 0000001A EXTI9_5_IRQHandler + 253 0000001A TIM1_BRK_IRQHandler + 254 0000001A TIM1_UP_IRQHandler + 255 0000001A TIM1_TRG_COM_IRQHandler + 256 0000001A TIM1_CC_IRQHandler + 257 0000001A TIM2_IRQHandler + 258 0000001A TIM3_IRQHandler + 259 0000001A TIM4_IRQHandler + 260 0000001A I2C1_EV_IRQHandler + 261 0000001A I2C1_ER_IRQHandler + 262 0000001A I2C2_EV_IRQHandler + 263 0000001A I2C2_ER_IRQHandler + 264 0000001A SPI1_IRQHandler + 265 0000001A SPI2_IRQHandler + 266 0000001A USART1_IRQHandler + 267 0000001A USART2_IRQHandler + 268 0000001A USART3_IRQHandler + 269 0000001A EXTI15_10_IRQHandler + 270 0000001A RTCAlarm_IRQHandler + 271 0000001A USBWakeUp_IRQHandler + 272 0000001A + 273 0000001A E7FE B . + 274 0000001C + 275 0000001C ENDP + 276 0000001C + 277 0000001C ALIGN + 278 0000001C + 279 0000001C ;******************************************************* + ************************ + 280 0000001C ; User Stack and Heap initialization + 281 0000001C ;******************************************************* + ************************ + 282 0000001C IF :DEF:__MICROLIB + 283 0000001C + 284 0000001C EXPORT __initial_sp + 285 0000001C EXPORT __heap_base + 286 0000001C EXPORT __heap_limit + 287 0000001C + 288 0000001C ELSE + 303 ENDIF + + + +ARM Macro Assembler Page 8 + + + 304 0000001C + 305 0000001C END + 00000000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=stm32-keil-unity\startup_stm32f10x_md.d -ostm32-keil-unity\startup +_stm32f10x_md.o -I.\RTE\Compiler -I.\RTE\Device\STM32F103RB -I.\RTE\_Test -IC:\ +Users\Owner\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Use +rs\Owner\AppData\Local\Arm\Packs\Keil\ARM_Compiler\1.6.2\Include -IC:\Users\Own +er\AppData\Local\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --predefine= +"__MICROLIB SETA 1" --predefine="__UVISION_VERSION SETA 529" --predefine="_RTE_ + SETA 1" --predefine="STM32F10X_MD SETA 1" --list=startup_stm32f10x_md.lst RTE\ +Device\STM32F103RB\startup_stm32f10x_md.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 35 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 37 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 284 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 46 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 47 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 285 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: __heap_base used once +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 49 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 286 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 56 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 61 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 57 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +__Vectors_End 000000EC + +Symbol: __Vectors_End + Definitions + At line 122 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 58 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 126 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: .text unused +ADC1_2_IRQHandler 0000001A + +Symbol: ADC1_2_IRQHandler + Definitions + At line 247 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 97 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 203 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 156 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 66 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 157 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 250 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 100 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 206 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +CAN1_SCE_IRQHandler 0000001A + +Symbol: CAN1_SCE_IRQHandler + Definitions + At line 251 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 101 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 207 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel1_IRQHandler 0000001A + +Symbol: DMA1_Channel1_IRQHandler + Definitions + At line 240 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 90 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 196 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel2_IRQHandler 0000001A + +Symbol: DMA1_Channel2_IRQHandler + Definitions + At line 241 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 91 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 197 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel3_IRQHandler 0000001A + +Symbol: DMA1_Channel3_IRQHandler + Definitions + At line 242 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 92 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 198 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel4_IRQHandler 0000001A + +Symbol: DMA1_Channel4_IRQHandler + Definitions + At line 243 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 93 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 199 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel5_IRQHandler 0000001A + +Symbol: DMA1_Channel5_IRQHandler + Definitions + At line 244 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 94 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 200 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel6_IRQHandler 0000001A + +Symbol: DMA1_Channel6_IRQHandler + Definitions + At line 245 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 95 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 201 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DMA1_Channel7_IRQHandler 0000001A + +Symbol: DMA1_Channel7_IRQHandler + Definitions + At line 246 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 96 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 202 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 170 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 73 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 171 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +Default_Handler 0000001A + + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + +Symbol: Default_Handler + Definitions + At line 183 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + None +Comment: Default_Handler unused +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 235 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 85 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 191 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI15_10_IRQHandler 0000001A + +Symbol: EXTI15_10_IRQHandler + Definitions + At line 269 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 119 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 225 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 236 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 86 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 192 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 237 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 87 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 193 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 238 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 88 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 194 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 239 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 89 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 195 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + +EXTI9_5_IRQHandler 0000001A + +Symbol: EXTI9_5_IRQHandler + Definitions + At line 252 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 102 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 208 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +FLASH_IRQHandler 0000001A + +Symbol: FLASH_IRQHandler + Definitions + At line 233 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 83 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 189 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 146 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 64 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 147 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 261 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 111 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 217 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +I2C1_EV_IRQHandler 0000001A + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 260 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 110 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 216 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +I2C2_ER_IRQHandler 0000001A + +Symbol: I2C2_ER_IRQHandler + Definitions + At line 263 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 113 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 219 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +I2C2_EV_IRQHandler 0000001A + +Symbol: I2C2_EV_IRQHandler + Definitions + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + At line 262 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 112 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 218 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 151 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 65 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 152 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 141 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 63 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 142 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +PVD_IRQHandler 0000001A + +Symbol: PVD_IRQHandler + Definitions + At line 230 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 80 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 186 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 174 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 75 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 175 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +RCC_IRQHandler 0000001A + +Symbol: RCC_IRQHandler + Definitions + At line 234 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 84 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 190 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +RTCAlarm_IRQHandler 0000001A + +Symbol: RTCAlarm_IRQHandler + Definitions + At line 270 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 120 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 226 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +RTC_IRQHandler 0000001A + +Symbol: RTC_IRQHandler + Definitions + At line 232 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 82 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 188 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 129 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 62 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 130 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 264 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 114 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 220 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 265 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 115 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 221 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 165 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 72 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 166 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 178 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 76 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 179 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TAMPER_IRQHandler 0000001A + +Symbol: TAMPER_IRQHandler + Definitions + At line 231 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 81 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 187 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM1_BRK_IRQHandler 0000001A + +Symbol: TIM1_BRK_IRQHandler + Definitions + At line 253 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 103 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 209 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM1_CC_IRQHandler 0000001A + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 256 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 106 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 212 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM1_TRG_COM_IRQHandler 0000001A + +Symbol: TIM1_TRG_COM_IRQHandler + Definitions + At line 255 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 105 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 211 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM1_UP_IRQHandler 0000001A + +Symbol: TIM1_UP_IRQHandler + Definitions + At line 254 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 104 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 210 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM2_IRQHandler 0000001A + +Symbol: TIM2_IRQHandler + Definitions + At line 257 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 107 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 213 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM3_IRQHandler 0000001A + +Symbol: TIM3_IRQHandler + Definitions + At line 258 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 108 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 214 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +TIM4_IRQHandler 0000001A + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: TIM4_IRQHandler + Definitions + At line 259 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 109 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 215 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 266 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 116 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 222 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 267 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 117 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 223 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USART3_IRQHandler 0000001A + +Symbol: USART3_IRQHandler + Definitions + At line 268 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 118 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 224 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USBWakeUp_IRQHandler 0000001A + +Symbol: USBWakeUp_IRQHandler + Definitions + At line 271 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 121 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 227 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USB_HP_CAN1_TX_IRQHandler 0000001A + +Symbol: USB_HP_CAN1_TX_IRQHandler + Definitions + At line 248 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 98 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 204 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +USB_LP_CAN1_RX0_IRQHandler 0000001A + +Symbol: USB_LP_CAN1_RX0_IRQHandler + Definitions + At line 249 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + + At line 99 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 205 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 161 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 67 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 162 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +WWDG_IRQHandler 0000001A + +Symbol: WWDG_IRQHandler + Definitions + At line 229 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 79 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + At line 185 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + +55 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 44 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 48 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: Heap_Size used once +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 33 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 36 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: Stack_Size used once +__Vectors_Size 000000EC + +Symbol: __Vectors_Size + Definitions + At line 124 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 59 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 132 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 133 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 131 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s + Uses + At line 135 in file RTE\Device\STM32F103RB\startup_stm32f10x_md.s +Comment: __main used once +2 symbols +406 symbols in table diff --git a/MDK-ARM/startup_stm32f429xx.lst b/MDK-ARM/startup_stm32f429xx.lst new file mode 100644 index 0000000..b0edf3f --- /dev/null +++ b/MDK-ARM/startup_stm32f429xx.lst @@ -0,0 +1,2091 @@ + + + +ARM Macro Assembler Page 1 + + + 1 00000000 ;******************** (C) COPYRIGHT 2016 STMicroelectron + ics ******************** + 2 00000000 ;* File Name : startup_stm32f429xx.s + 3 00000000 ;* Author : MCD Application Team + 4 00000000 ;* Version : V2.5.0 + 5 00000000 ;* Date : 22-April-2016 + 6 00000000 ;* Description : STM32F429x devices vector table + for MDK-ARM toolchain. + 7 00000000 ;* This module performs: + 8 00000000 ;* - Set the initial SP + 9 00000000 ;* - Set the initial PC == Reset_Ha + ndler + 10 00000000 ;* - Set the vector table entries w + ith the exceptions ISR address + 11 00000000 ;* - Branches to __main in the C li + brary (which eventually + 12 00000000 ;* calls main()). + 13 00000000 ;* After Reset the CortexM4 process + or is in Thread mode, + 14 00000000 ;* priority is Privileged, and the + Stack is set to Main. + 15 00000000 ;* <<< Use Configuration Wizard in Context Menu >>> + 16 00000000 ;******************************************************* + ************************ + 17 00000000 ; + 18 00000000 ;* Redistribution and use in source and binary forms, wi + th or without modification, + 19 00000000 ;* are permitted provided that the following conditions + are met: + 20 00000000 ;* 1. Redistributions of source code must retain the a + bove copyright notice, + 21 00000000 ;* this list of conditions and the following discla + imer. + 22 00000000 ;* 2. Redistributions in binary form must reproduce th + e above copyright notice, + 23 00000000 ;* this list of conditions and the following discla + imer in the documentation + 24 00000000 ;* and/or other materials provided with the distrib + ution. + 25 00000000 ;* 3. Neither the name of STMicroelectronics nor the n + ames of its contributors + 26 00000000 ;* may be used to endorse or promote products deriv + ed from this software + 27 00000000 ;* without specific prior written permission. + 28 00000000 ;* + 29 00000000 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AN + D CONTRIBUTORS "AS IS" + 30 00000000 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT + NOT LIMITED TO, THE + 31 00000000 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE + 32 00000000 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + CONTRIBUTORS BE LIABLE + 33 00000000 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPL + ARY, OR CONSEQUENTIAL + 34 00000000 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT O + F SUBSTITUTE GOODS OR + 35 00000000 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER + + + +ARM Macro Assembler Page 2 + + + 36 00000000 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CON + TRACT, STRICT LIABILITY, + 37 00000000 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING I + N ANY WAY OUT OF THE USE + 38 00000000 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + OF SUCH DAMAGE. + 39 00000000 ; + 40 00000000 ;******************************************************* + ************************ + 41 00000000 + 42 00000000 ; Amount of memory (in bytes) allocated for Stack + 43 00000000 ; Tailor this value to your application needs + 44 00000000 ; Stack Configuration + 45 00000000 ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + 46 00000000 ; + 47 00000000 + 48 00000000 00000400 + Stack_Size + EQU 0x400 + 49 00000000 + 50 00000000 AREA STACK, NOINIT, READWRITE, ALIGN +=3 + 51 00000000 Stack_Mem + SPACE Stack_Size + 52 00000400 __initial_sp + 53 00000400 + 54 00000400 + 55 00000400 ; Heap Configuration + 56 00000400 ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + 57 00000400 ; + 58 00000400 + 59 00000400 00000200 + Heap_Size + EQU 0x200 + 60 00000400 + 61 00000400 AREA HEAP, NOINIT, READWRITE, ALIGN= +3 + 62 00000000 __heap_base + 63 00000000 Heap_Mem + SPACE Heap_Size + 64 00000200 __heap_limit + 65 00000200 + 66 00000200 PRESERVE8 + 67 00000200 THUMB + 68 00000200 + 69 00000200 + 70 00000200 ; Vector Table Mapped to Address 0 at Reset + 71 00000200 AREA RESET, DATA, READONLY + 72 00000000 EXPORT __Vectors + 73 00000000 EXPORT __Vectors_End + 74 00000000 EXPORT __Vectors_Size + 75 00000000 + 76 00000000 00000000 + __Vectors + DCD __initial_sp ; Top of Stack + 77 00000004 00000000 DCD Reset_Handler ; Reset Handler + 78 00000008 00000000 DCD NMI_Handler ; NMI Handler + 79 0000000C 00000000 DCD HardFault_Handler ; Hard Fault + Handler + + + +ARM Macro Assembler Page 3 + + + 80 00000010 00000000 DCD MemManage_Handler + ; MPU Fault Handler + + 81 00000014 00000000 DCD BusFault_Handler + ; Bus Fault Handler + + 82 00000018 00000000 DCD UsageFault_Handler ; Usage Faul + t Handler + 83 0000001C 00000000 DCD 0 ; Reserved + 84 00000020 00000000 DCD 0 ; Reserved + 85 00000024 00000000 DCD 0 ; Reserved + 86 00000028 00000000 DCD 0 ; Reserved + 87 0000002C 00000000 DCD SVC_Handler ; SVCall Handler + 88 00000030 00000000 DCD DebugMon_Handler ; Debug Monito + r Handler + 89 00000034 00000000 DCD 0 ; Reserved + 90 00000038 00000000 DCD PendSV_Handler ; PendSV Handler + + 91 0000003C 00000000 DCD SysTick_Handler + ; SysTick Handler + 92 00000040 + 93 00000040 ; External Interrupts + 94 00000040 00000000 DCD WWDG_IRQHandler ; Window WatchD + og + + + 95 00000044 00000000 DCD PVD_IRQHandler ; PVD through EX + TI Line detection + + + 96 00000048 00000000 DCD TAMP_STAMP_IRQHandler ; Tamper + and TimeStamps thro + ugh the EXTI line + + 97 0000004C 00000000 DCD RTC_WKUP_IRQHandler ; RTC Wakeu + p through the EXTI + line + + 98 00000050 00000000 DCD FLASH_IRQHandler ; FLASH + + + 99 00000054 00000000 DCD RCC_IRQHandler ; RCC + + + 100 00000058 00000000 DCD EXTI0_IRQHandler ; EXTI Line0 + + + + 101 0000005C 00000000 DCD EXTI1_IRQHandler ; EXTI Line1 + + + + 102 00000060 00000000 DCD EXTI2_IRQHandler ; EXTI Line2 + + + + 103 00000064 00000000 DCD EXTI3_IRQHandler ; EXTI Line3 + + + + + +ARM Macro Assembler Page 4 + + + + 104 00000068 00000000 DCD EXTI4_IRQHandler ; EXTI Line4 + + + + 105 0000006C 00000000 DCD DMA1_Stream0_IRQHandler ; DMA1 + Stream 0 + + + 106 00000070 00000000 DCD DMA1_Stream1_IRQHandler ; DMA1 + Stream 1 + + + 107 00000074 00000000 DCD DMA1_Stream2_IRQHandler ; DMA1 + Stream 2 + + + 108 00000078 00000000 DCD DMA1_Stream3_IRQHandler ; DMA1 + Stream 3 + + + 109 0000007C 00000000 DCD DMA1_Stream4_IRQHandler ; DMA1 + Stream 4 + + + 110 00000080 00000000 DCD DMA1_Stream5_IRQHandler ; DMA1 + Stream 5 + + + 111 00000084 00000000 DCD DMA1_Stream6_IRQHandler ; DMA1 + Stream 6 + + + 112 00000088 00000000 DCD ADC_IRQHandler ; ADC1, ADC2 and + ADC3s + + 113 0000008C 00000000 DCD CAN1_TX_IRQHandler ; CAN1 TX + + + + 114 00000090 00000000 DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + + + + 115 00000094 00000000 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + + + + 116 00000098 00000000 DCD CAN1_SCE_IRQHandler ; CAN1 SCE + + + + 117 0000009C 00000000 DCD EXTI9_5_IRQHandler ; External L + ine[9:5]s + + + 118 000000A0 00000000 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 + Break and TIM9 + + + + +ARM Macro Assembler Page 5 + + + 119 000000A4 00000000 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 + Update and TIM10 + + 120 000000A8 00000000 DCD TIM1_TRG_COM_TIM11_IRQHandler ; + TIM1 Trigger and C + ommutation and TIM1 + 1 + 121 000000AC 00000000 DCD TIM1_CC_IRQHandler ; TIM1 Captu + re Compare + + + 122 000000B0 00000000 DCD TIM2_IRQHandler ; TIM2 + + + 123 000000B4 00000000 DCD TIM3_IRQHandler ; TIM3 + + + 124 000000B8 00000000 DCD TIM4_IRQHandler ; TIM4 + + + 125 000000BC 00000000 DCD I2C1_EV_IRQHandler ; I2C1 Event + + + + 126 000000C0 00000000 DCD I2C1_ER_IRQHandler ; I2C1 Error + + + + 127 000000C4 00000000 DCD I2C2_EV_IRQHandler ; I2C2 Event + + + + 128 000000C8 00000000 DCD I2C2_ER_IRQHandler ; I2C2 Error + + + + 129 000000CC 00000000 DCD SPI1_IRQHandler ; SPI1 + + + 130 000000D0 00000000 DCD SPI2_IRQHandler ; SPI2 + + + 131 000000D4 00000000 DCD USART1_IRQHandler ; USART1 + + + 132 000000D8 00000000 DCD USART2_IRQHandler ; USART2 + + + 133 000000DC 00000000 DCD USART3_IRQHandler ; USART3 + + + 134 000000E0 00000000 DCD EXTI15_10_IRQHandler ; External + Line[15:10]s + + + 135 000000E4 00000000 DCD RTC_Alarm_IRQHandler ; RTC Alar + m (A and B) through + EXTI Line + + + + +ARM Macro Assembler Page 6 + + + 136 000000E8 00000000 DCD OTG_FS_WKUP_IRQHandler ; USB OT + G FS Wakeup through + EXTI line + + 137 000000EC 00000000 DCD TIM8_BRK_TIM12_IRQHandler ; TIM + 8 Break and TIM12 + + 138 000000F0 00000000 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 + Update and TIM13 + + 139 000000F4 00000000 DCD TIM8_TRG_COM_TIM14_IRQHandler ; + TIM8 Trigger and C + ommutation and TIM1 + 4 + 140 000000F8 00000000 DCD TIM8_CC_IRQHandler ; TIM8 Captu + re Compare + + + 141 000000FC 00000000 DCD DMA1_Stream7_IRQHandler ; DMA1 + Stream7 + + + 142 00000100 00000000 DCD FMC_IRQHandler ; FMC + + + 143 00000104 00000000 DCD SDIO_IRQHandler ; SDIO + + + 144 00000108 00000000 DCD TIM5_IRQHandler ; TIM5 + + + 145 0000010C 00000000 DCD SPI3_IRQHandler ; SPI3 + + + 146 00000110 00000000 DCD UART4_IRQHandler ; UART4 + + + 147 00000114 00000000 DCD UART5_IRQHandler ; UART5 + + + 148 00000118 00000000 DCD TIM6_DAC_IRQHandler ; TIM6 and + DAC1&2 underrun err + ors + + 149 0000011C 00000000 DCD TIM7_IRQHandler ; TIM7 + + 150 00000120 00000000 DCD DMA2_Stream0_IRQHandler ; DMA2 + Stream 0 + + + 151 00000124 00000000 DCD DMA2_Stream1_IRQHandler ; DMA2 + Stream 1 + + + 152 00000128 00000000 DCD DMA2_Stream2_IRQHandler ; DMA2 + Stream 2 + + + 153 0000012C 00000000 DCD DMA2_Stream3_IRQHandler ; DMA2 + + + +ARM Macro Assembler Page 7 + + + Stream 3 + + + 154 00000130 00000000 DCD DMA2_Stream4_IRQHandler ; DMA2 + Stream 4 + + + 155 00000134 00000000 DCD ETH_IRQHandler ; Ethernet + + + 156 00000138 00000000 DCD ETH_WKUP_IRQHandler ; Ethernet + Wakeup through EXTI + line + + 157 0000013C 00000000 DCD CAN2_TX_IRQHandler ; CAN2 TX + + + + 158 00000140 00000000 DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + + + + 159 00000144 00000000 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + + + + 160 00000148 00000000 DCD CAN2_SCE_IRQHandler ; CAN2 SCE + + + + 161 0000014C 00000000 DCD OTG_FS_IRQHandler ; USB OTG FS + + + 162 00000150 00000000 DCD DMA2_Stream5_IRQHandler ; DMA2 + Stream 5 + + + 163 00000154 00000000 DCD DMA2_Stream6_IRQHandler ; DMA2 + Stream 6 + + + 164 00000158 00000000 DCD DMA2_Stream7_IRQHandler ; DMA2 + Stream 7 + + + 165 0000015C 00000000 DCD USART6_IRQHandler ; USART6 + + + + 166 00000160 00000000 DCD I2C3_EV_IRQHandler ; I2C3 event + + + + 167 00000164 00000000 DCD I2C3_ER_IRQHandler ; I2C3 error + + + + 168 00000168 00000000 DCD OTG_HS_EP1_OUT_IRQHandler ; USB + OTG HS End Point 1 + + + +ARM Macro Assembler Page 8 + + + Out + + 169 0000016C 00000000 DCD OTG_HS_EP1_IN_IRQHandler ; USB + OTG HS End Point 1 + In + + 170 00000170 00000000 DCD OTG_HS_WKUP_IRQHandler ; USB OT + G HS Wakeup through + EXTI + + 171 00000174 00000000 DCD OTG_HS_IRQHandler ; USB OTG HS + + + 172 00000178 00000000 DCD DCMI_IRQHandler ; DCMI + 173 0000017C 00000000 DCD 0 ; Reserved + + + 174 00000180 00000000 DCD HASH_RNG_IRQHandler + ; Hash and Rng + 175 00000184 00000000 DCD FPU_IRQHandler ; FPU + 176 00000188 00000000 DCD UART7_IRQHandler ; UART7 + 177 0000018C 00000000 DCD UART8_IRQHandler ; UART8 + 178 00000190 00000000 DCD SPI4_IRQHandler ; SPI4 + 179 00000194 00000000 DCD SPI5_IRQHandler ; SPI5 + 180 00000198 00000000 DCD SPI6_IRQHandler ; SPI6 + 181 0000019C 00000000 DCD SAI1_IRQHandler ; SAI1 + 182 000001A0 00000000 DCD LTDC_IRQHandler ; LTDC + 183 000001A4 00000000 DCD LTDC_ER_IRQHandler ; LTDC error + + 184 000001A8 00000000 DCD DMA2D_IRQHandler ; DMA2D + 185 000001AC + 186 000001AC __Vectors_End + 187 000001AC + 188 000001AC 000001AC + __Vectors_Size + EQU __Vectors_End - __Vectors + 189 000001AC + 190 000001AC AREA |.text|, CODE, READONLY + 191 00000000 + 192 00000000 ; Reset handler + 193 00000000 Reset_Handler + PROC + 194 00000000 EXPORT Reset_Handler [WEAK +] + 195 00000000 IMPORT SystemInit + 196 00000000 IMPORT __main + 197 00000000 + 198 00000000 4806 LDR R0, =SystemInit + 199 00000002 4780 BLX R0 + 200 00000004 4806 LDR R0, =__main + 201 00000006 4700 BX R0 + 202 00000008 ENDP + 203 00000008 + 204 00000008 ; Dummy Exception Handlers (infinite loops which can be + modified) + 205 00000008 + 206 00000008 NMI_Handler + PROC + 207 00000008 EXPORT NMI_Handler [WEA + + + +ARM Macro Assembler Page 9 + + +K] + 208 00000008 E7FE B . + 209 0000000A ENDP + 211 0000000A HardFault_Handler + PROC + 212 0000000A EXPORT HardFault_Handler [WEA +K] + 213 0000000A E7FE B . + 214 0000000C ENDP + 216 0000000C MemManage_Handler + PROC + 217 0000000C EXPORT MemManage_Handler [WEA +K] + 218 0000000C E7FE B . + 219 0000000E ENDP + 221 0000000E BusFault_Handler + PROC + 222 0000000E EXPORT BusFault_Handler [WEA +K] + 223 0000000E E7FE B . + 224 00000010 ENDP + 226 00000010 UsageFault_Handler + PROC + 227 00000010 EXPORT UsageFault_Handler [WEA +K] + 228 00000010 E7FE B . + 229 00000012 ENDP + 230 00000012 SVC_Handler + PROC + 231 00000012 EXPORT SVC_Handler [WEA +K] + 232 00000012 E7FE B . + 233 00000014 ENDP + 235 00000014 DebugMon_Handler + PROC + 236 00000014 EXPORT DebugMon_Handler [WEA +K] + 237 00000014 E7FE B . + 238 00000016 ENDP + 239 00000016 PendSV_Handler + PROC + 240 00000016 EXPORT PendSV_Handler [WEA +K] + 241 00000016 E7FE B . + 242 00000018 ENDP + 243 00000018 SysTick_Handler + PROC + 244 00000018 EXPORT SysTick_Handler [WEA +K] + 245 00000018 E7FE B . + 246 0000001A ENDP + 247 0000001A + 248 0000001A Default_Handler + PROC + 249 0000001A + 250 0000001A EXPORT WWDG_IRQHandler + [WEAK] + 251 0000001A EXPORT PVD_IRQHandler + [WEAK] + + + +ARM Macro Assembler Page 10 + + + 252 0000001A EXPORT TAMP_STAMP_IRQHandler + [WEAK] + 253 0000001A EXPORT RTC_WKUP_IRQHandler + [WEAK] + 254 0000001A EXPORT FLASH_IRQHandler + [WEAK] + 255 0000001A EXPORT RCC_IRQHandler + [WEAK] + 256 0000001A EXPORT EXTI0_IRQHandler + [WEAK] + 257 0000001A EXPORT EXTI1_IRQHandler + [WEAK] + 258 0000001A EXPORT EXTI2_IRQHandler + [WEAK] + 259 0000001A EXPORT EXTI3_IRQHandler + [WEAK] + 260 0000001A EXPORT EXTI4_IRQHandler + [WEAK] + 261 0000001A EXPORT DMA1_Stream0_IRQHandler + [WEAK] + 262 0000001A EXPORT DMA1_Stream1_IRQHandler + [WEAK] + 263 0000001A EXPORT DMA1_Stream2_IRQHandler + [WEAK] + 264 0000001A EXPORT DMA1_Stream3_IRQHandler + [WEAK] + 265 0000001A EXPORT DMA1_Stream4_IRQHandler + [WEAK] + 266 0000001A EXPORT DMA1_Stream5_IRQHandler + [WEAK] + 267 0000001A EXPORT DMA1_Stream6_IRQHandler + [WEAK] + 268 0000001A EXPORT ADC_IRQHandler + [WEAK] + 269 0000001A EXPORT CAN1_TX_IRQHandler + [WEAK] + 270 0000001A EXPORT CAN1_RX0_IRQHandler + [WEAK] + 271 0000001A EXPORT CAN1_RX1_IRQHandler + [WEAK] + 272 0000001A EXPORT CAN1_SCE_IRQHandler + [WEAK] + 273 0000001A EXPORT EXTI9_5_IRQHandler + [WEAK] + 274 0000001A EXPORT TIM1_BRK_TIM9_IRQHandler + [WEAK] + 275 0000001A EXPORT TIM1_UP_TIM10_IRQHandler + [WEAK] + 276 0000001A EXPORT TIM1_TRG_COM_TIM11_IRQHandler + [WEAK] + 277 0000001A EXPORT TIM1_CC_IRQHandler + [WEAK] + 278 0000001A EXPORT TIM2_IRQHandler + [WEAK] + 279 0000001A EXPORT TIM3_IRQHandler + [WEAK] + 280 0000001A EXPORT TIM4_IRQHandler + [WEAK] + 281 0000001A EXPORT I2C1_EV_IRQHandler + + + +ARM Macro Assembler Page 11 + + + [WEAK] + 282 0000001A EXPORT I2C1_ER_IRQHandler + [WEAK] + 283 0000001A EXPORT I2C2_EV_IRQHandler + [WEAK] + 284 0000001A EXPORT I2C2_ER_IRQHandler + [WEAK] + 285 0000001A EXPORT SPI1_IRQHandler + [WEAK] + 286 0000001A EXPORT SPI2_IRQHandler + [WEAK] + 287 0000001A EXPORT USART1_IRQHandler + [WEAK] + 288 0000001A EXPORT USART2_IRQHandler + [WEAK] + 289 0000001A EXPORT USART3_IRQHandler + [WEAK] + 290 0000001A EXPORT EXTI15_10_IRQHandler + [WEAK] + 291 0000001A EXPORT RTC_Alarm_IRQHandler + [WEAK] + 292 0000001A EXPORT OTG_FS_WKUP_IRQHandler + [WEAK] + 293 0000001A EXPORT TIM8_BRK_TIM12_IRQHandler + [WEAK] + 294 0000001A EXPORT TIM8_UP_TIM13_IRQHandler + [WEAK] + 295 0000001A EXPORT TIM8_TRG_COM_TIM14_IRQHandler + [WEAK] + 296 0000001A EXPORT TIM8_CC_IRQHandler + [WEAK] + 297 0000001A EXPORT DMA1_Stream7_IRQHandler + [WEAK] + 298 0000001A EXPORT FMC_IRQHandler + [WEAK] + 299 0000001A EXPORT SDIO_IRQHandler + [WEAK] + 300 0000001A EXPORT TIM5_IRQHandler + [WEAK] + 301 0000001A EXPORT SPI3_IRQHandler + [WEAK] + 302 0000001A EXPORT UART4_IRQHandler + [WEAK] + 303 0000001A EXPORT UART5_IRQHandler + [WEAK] + 304 0000001A EXPORT TIM6_DAC_IRQHandler + [WEAK] + 305 0000001A EXPORT TIM7_IRQHandler + [WEAK] + 306 0000001A EXPORT DMA2_Stream0_IRQHandler + [WEAK] + 307 0000001A EXPORT DMA2_Stream1_IRQHandler + [WEAK] + 308 0000001A EXPORT DMA2_Stream2_IRQHandler + [WEAK] + 309 0000001A EXPORT DMA2_Stream3_IRQHandler + [WEAK] + 310 0000001A EXPORT DMA2_Stream4_IRQHandler + [WEAK] + + + +ARM Macro Assembler Page 12 + + + 311 0000001A EXPORT ETH_IRQHandler + [WEAK] + 312 0000001A EXPORT ETH_WKUP_IRQHandler + [WEAK] + 313 0000001A EXPORT CAN2_TX_IRQHandler + [WEAK] + 314 0000001A EXPORT CAN2_RX0_IRQHandler + [WEAK] + 315 0000001A EXPORT CAN2_RX1_IRQHandler + [WEAK] + 316 0000001A EXPORT CAN2_SCE_IRQHandler + [WEAK] + 317 0000001A EXPORT OTG_FS_IRQHandler + [WEAK] + 318 0000001A EXPORT DMA2_Stream5_IRQHandler + [WEAK] + 319 0000001A EXPORT DMA2_Stream6_IRQHandler + [WEAK] + 320 0000001A EXPORT DMA2_Stream7_IRQHandler + [WEAK] + 321 0000001A EXPORT USART6_IRQHandler + [WEAK] + 322 0000001A EXPORT I2C3_EV_IRQHandler + [WEAK] + 323 0000001A EXPORT I2C3_ER_IRQHandler + [WEAK] + 324 0000001A EXPORT OTG_HS_EP1_OUT_IRQHandler + [WEAK] + 325 0000001A EXPORT OTG_HS_EP1_IN_IRQHandler + [WEAK] + 326 0000001A EXPORT OTG_HS_WKUP_IRQHandler + [WEAK] + 327 0000001A EXPORT OTG_HS_IRQHandler + [WEAK] + 328 0000001A EXPORT DCMI_IRQHandler + [WEAK] + 329 0000001A EXPORT HASH_RNG_IRQHandler + [WEAK] + 330 0000001A EXPORT FPU_IRQHandler + [WEAK] + 331 0000001A EXPORT UART7_IRQHandler + [WEAK] + 332 0000001A EXPORT UART8_IRQHandler + [WEAK] + 333 0000001A EXPORT SPI4_IRQHandler + [WEAK] + 334 0000001A EXPORT SPI5_IRQHandler + [WEAK] + 335 0000001A EXPORT SPI6_IRQHandler + [WEAK] + 336 0000001A EXPORT SAI1_IRQHandler + [WEAK] + 337 0000001A EXPORT LTDC_IRQHandler + [WEAK] + 338 0000001A EXPORT LTDC_ER_IRQHandler + [WEAK] + 339 0000001A EXPORT DMA2D_IRQHandler + [WEAK] + 340 0000001A + + + +ARM Macro Assembler Page 13 + + + 341 0000001A WWDG_IRQHandler + 342 0000001A PVD_IRQHandler + 343 0000001A TAMP_STAMP_IRQHandler + 344 0000001A RTC_WKUP_IRQHandler + 345 0000001A FLASH_IRQHandler + 346 0000001A RCC_IRQHandler + 347 0000001A EXTI0_IRQHandler + 348 0000001A EXTI1_IRQHandler + 349 0000001A EXTI2_IRQHandler + 350 0000001A EXTI3_IRQHandler + 351 0000001A EXTI4_IRQHandler + 352 0000001A DMA1_Stream0_IRQHandler + 353 0000001A DMA1_Stream1_IRQHandler + 354 0000001A DMA1_Stream2_IRQHandler + 355 0000001A DMA1_Stream3_IRQHandler + 356 0000001A DMA1_Stream4_IRQHandler + 357 0000001A DMA1_Stream5_IRQHandler + 358 0000001A DMA1_Stream6_IRQHandler + 359 0000001A ADC_IRQHandler + 360 0000001A CAN1_TX_IRQHandler + 361 0000001A CAN1_RX0_IRQHandler + 362 0000001A CAN1_RX1_IRQHandler + 363 0000001A CAN1_SCE_IRQHandler + 364 0000001A EXTI9_5_IRQHandler + 365 0000001A TIM1_BRK_TIM9_IRQHandler + 366 0000001A TIM1_UP_TIM10_IRQHandler + 367 0000001A TIM1_TRG_COM_TIM11_IRQHandler + 368 0000001A TIM1_CC_IRQHandler + 369 0000001A TIM2_IRQHandler + 370 0000001A TIM3_IRQHandler + 371 0000001A TIM4_IRQHandler + 372 0000001A I2C1_EV_IRQHandler + 373 0000001A I2C1_ER_IRQHandler + 374 0000001A I2C2_EV_IRQHandler + 375 0000001A I2C2_ER_IRQHandler + 376 0000001A SPI1_IRQHandler + 377 0000001A SPI2_IRQHandler + 378 0000001A USART1_IRQHandler + 379 0000001A USART2_IRQHandler + 380 0000001A USART3_IRQHandler + 381 0000001A EXTI15_10_IRQHandler + 382 0000001A RTC_Alarm_IRQHandler + 383 0000001A OTG_FS_WKUP_IRQHandler + 384 0000001A TIM8_BRK_TIM12_IRQHandler + 385 0000001A TIM8_UP_TIM13_IRQHandler + 386 0000001A TIM8_TRG_COM_TIM14_IRQHandler + 387 0000001A TIM8_CC_IRQHandler + 388 0000001A DMA1_Stream7_IRQHandler + 389 0000001A FMC_IRQHandler + 390 0000001A SDIO_IRQHandler + 391 0000001A TIM5_IRQHandler + 392 0000001A SPI3_IRQHandler + 393 0000001A UART4_IRQHandler + 394 0000001A UART5_IRQHandler + 395 0000001A TIM6_DAC_IRQHandler + 396 0000001A TIM7_IRQHandler + 397 0000001A DMA2_Stream0_IRQHandler + 398 0000001A DMA2_Stream1_IRQHandler + 399 0000001A DMA2_Stream2_IRQHandler + + + +ARM Macro Assembler Page 14 + + + 400 0000001A DMA2_Stream3_IRQHandler + 401 0000001A DMA2_Stream4_IRQHandler + 402 0000001A ETH_IRQHandler + 403 0000001A ETH_WKUP_IRQHandler + 404 0000001A CAN2_TX_IRQHandler + 405 0000001A CAN2_RX0_IRQHandler + 406 0000001A CAN2_RX1_IRQHandler + 407 0000001A CAN2_SCE_IRQHandler + 408 0000001A OTG_FS_IRQHandler + 409 0000001A DMA2_Stream5_IRQHandler + 410 0000001A DMA2_Stream6_IRQHandler + 411 0000001A DMA2_Stream7_IRQHandler + 412 0000001A USART6_IRQHandler + 413 0000001A I2C3_EV_IRQHandler + 414 0000001A I2C3_ER_IRQHandler + 415 0000001A OTG_HS_EP1_OUT_IRQHandler + 416 0000001A OTG_HS_EP1_IN_IRQHandler + 417 0000001A OTG_HS_WKUP_IRQHandler + 418 0000001A OTG_HS_IRQHandler + 419 0000001A DCMI_IRQHandler + 420 0000001A HASH_RNG_IRQHandler + 421 0000001A FPU_IRQHandler + 422 0000001A UART7_IRQHandler + 423 0000001A UART8_IRQHandler + 424 0000001A SPI4_IRQHandler + 425 0000001A SPI5_IRQHandler + 426 0000001A SPI6_IRQHandler + 427 0000001A SAI1_IRQHandler + 428 0000001A LTDC_IRQHandler + 429 0000001A LTDC_ER_IRQHandler + 430 0000001A DMA2D_IRQHandler + 431 0000001A E7FE B . + 432 0000001C + 433 0000001C ENDP + 434 0000001C + 435 0000001C ALIGN + 436 0000001C + 437 0000001C ;******************************************************* + ************************ + 438 0000001C ; User Stack and Heap initialization + 439 0000001C ;******************************************************* + ************************ + 440 0000001C IF :DEF:__MICROLIB + 441 0000001C + 442 0000001C EXPORT __initial_sp + 443 0000001C EXPORT __heap_base + 444 0000001C EXPORT __heap_limit + 445 0000001C + 446 0000001C ELSE + 461 ENDIF + 462 0000001C + 463 0000001C END + 00000000 + 00000000 +Command Line: --debug --xref --diag_suppress=9931 --cpu=Cortex-M3 --apcs=interw +ork --depend=stm32-keil-unity\startup_stm32f429xx.d -ostm32-keil-unity\startup_ +stm32f429xx.o -I.\RTE\Device\STM32F103RB -I.\RTE\_Test -IC:\Users\Owner\AppData +\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\Core\Include -IC:\Users\Owner\AppData\Lo +cal\Arm\Packs\Keil\STM32F1xx_DFP\2.3.0\Device\Include --predefine="__MICROLIB S + + + +ARM Macro Assembler Page 15 + + +ETA 1" --predefine="__UVISION_VERSION SETA 529" --predefine="_RTE_ SETA 1" --pr +edefine="STM32F10X_MD SETA 1" --list=startup_stm32f429xx.lst startup_stm32f429x +x.s + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +STACK 00000000 + +Symbol: STACK + Definitions + At line 50 in file startup_stm32f429xx.s + Uses + None +Comment: STACK unused +Stack_Mem 00000000 + +Symbol: Stack_Mem + Definitions + At line 51 in file startup_stm32f429xx.s + Uses + None +Comment: Stack_Mem unused +__initial_sp 00000400 + +Symbol: __initial_sp + Definitions + At line 52 in file startup_stm32f429xx.s + Uses + At line 76 in file startup_stm32f429xx.s + At line 442 in file startup_stm32f429xx.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +HEAP 00000000 + +Symbol: HEAP + Definitions + At line 61 in file startup_stm32f429xx.s + Uses + None +Comment: HEAP unused +Heap_Mem 00000000 + +Symbol: Heap_Mem + Definitions + At line 63 in file startup_stm32f429xx.s + Uses + None +Comment: Heap_Mem unused +__heap_base 00000000 + +Symbol: __heap_base + Definitions + At line 62 in file startup_stm32f429xx.s + Uses + At line 443 in file startup_stm32f429xx.s +Comment: __heap_base used once +__heap_limit 00000200 + +Symbol: __heap_limit + Definitions + At line 64 in file startup_stm32f429xx.s + Uses + At line 444 in file startup_stm32f429xx.s +Comment: __heap_limit used once +4 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +RESET 00000000 + +Symbol: RESET + Definitions + At line 71 in file startup_stm32f429xx.s + Uses + None +Comment: RESET unused +__Vectors 00000000 + +Symbol: __Vectors + Definitions + At line 76 in file startup_stm32f429xx.s + Uses + At line 72 in file startup_stm32f429xx.s + At line 188 in file startup_stm32f429xx.s + +__Vectors_End 000001AC + +Symbol: __Vectors_End + Definitions + At line 186 in file startup_stm32f429xx.s + Uses + At line 73 in file startup_stm32f429xx.s + At line 188 in file startup_stm32f429xx.s + +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Relocatable symbols + +.text 00000000 + +Symbol: .text + Definitions + At line 190 in file startup_stm32f429xx.s + Uses + None +Comment: .text unused +ADC_IRQHandler 0000001A + +Symbol: ADC_IRQHandler + Definitions + At line 359 in file startup_stm32f429xx.s + Uses + At line 112 in file startup_stm32f429xx.s + At line 268 in file startup_stm32f429xx.s + +BusFault_Handler 0000000E + +Symbol: BusFault_Handler + Definitions + At line 221 in file startup_stm32f429xx.s + Uses + At line 81 in file startup_stm32f429xx.s + At line 222 in file startup_stm32f429xx.s + +CAN1_RX0_IRQHandler 0000001A + +Symbol: CAN1_RX0_IRQHandler + Definitions + At line 361 in file startup_stm32f429xx.s + Uses + At line 114 in file startup_stm32f429xx.s + At line 270 in file startup_stm32f429xx.s + +CAN1_RX1_IRQHandler 0000001A + +Symbol: CAN1_RX1_IRQHandler + Definitions + At line 362 in file startup_stm32f429xx.s + Uses + At line 115 in file startup_stm32f429xx.s + At line 271 in file startup_stm32f429xx.s + +CAN1_SCE_IRQHandler 0000001A + +Symbol: CAN1_SCE_IRQHandler + Definitions + At line 363 in file startup_stm32f429xx.s + Uses + At line 116 in file startup_stm32f429xx.s + At line 272 in file startup_stm32f429xx.s + +CAN1_TX_IRQHandler 0000001A + +Symbol: CAN1_TX_IRQHandler + Definitions + At line 360 in file startup_stm32f429xx.s + Uses + + + +ARM Macro Assembler Page 2 Alphabetic symbol ordering +Relocatable symbols + + At line 113 in file startup_stm32f429xx.s + At line 269 in file startup_stm32f429xx.s + +CAN2_RX0_IRQHandler 0000001A + +Symbol: CAN2_RX0_IRQHandler + Definitions + At line 405 in file startup_stm32f429xx.s + Uses + At line 158 in file startup_stm32f429xx.s + At line 314 in file startup_stm32f429xx.s + +CAN2_RX1_IRQHandler 0000001A + +Symbol: CAN2_RX1_IRQHandler + Definitions + At line 406 in file startup_stm32f429xx.s + Uses + At line 159 in file startup_stm32f429xx.s + At line 315 in file startup_stm32f429xx.s + +CAN2_SCE_IRQHandler 0000001A + +Symbol: CAN2_SCE_IRQHandler + Definitions + At line 407 in file startup_stm32f429xx.s + Uses + At line 160 in file startup_stm32f429xx.s + At line 316 in file startup_stm32f429xx.s + +CAN2_TX_IRQHandler 0000001A + +Symbol: CAN2_TX_IRQHandler + Definitions + At line 404 in file startup_stm32f429xx.s + Uses + At line 157 in file startup_stm32f429xx.s + At line 313 in file startup_stm32f429xx.s + +DCMI_IRQHandler 0000001A + +Symbol: DCMI_IRQHandler + Definitions + At line 419 in file startup_stm32f429xx.s + Uses + At line 172 in file startup_stm32f429xx.s + At line 328 in file startup_stm32f429xx.s + +DMA1_Stream0_IRQHandler 0000001A + +Symbol: DMA1_Stream0_IRQHandler + Definitions + At line 352 in file startup_stm32f429xx.s + Uses + At line 105 in file startup_stm32f429xx.s + At line 261 in file startup_stm32f429xx.s + +DMA1_Stream1_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 3 Alphabetic symbol ordering +Relocatable symbols + +Symbol: DMA1_Stream1_IRQHandler + Definitions + At line 353 in file startup_stm32f429xx.s + Uses + At line 106 in file startup_stm32f429xx.s + At line 262 in file startup_stm32f429xx.s + +DMA1_Stream2_IRQHandler 0000001A + +Symbol: DMA1_Stream2_IRQHandler + Definitions + At line 354 in file startup_stm32f429xx.s + Uses + At line 107 in file startup_stm32f429xx.s + At line 263 in file startup_stm32f429xx.s + +DMA1_Stream3_IRQHandler 0000001A + +Symbol: DMA1_Stream3_IRQHandler + Definitions + At line 355 in file startup_stm32f429xx.s + Uses + At line 108 in file startup_stm32f429xx.s + At line 264 in file startup_stm32f429xx.s + +DMA1_Stream4_IRQHandler 0000001A + +Symbol: DMA1_Stream4_IRQHandler + Definitions + At line 356 in file startup_stm32f429xx.s + Uses + At line 109 in file startup_stm32f429xx.s + At line 265 in file startup_stm32f429xx.s + +DMA1_Stream5_IRQHandler 0000001A + +Symbol: DMA1_Stream5_IRQHandler + Definitions + At line 357 in file startup_stm32f429xx.s + Uses + At line 110 in file startup_stm32f429xx.s + At line 266 in file startup_stm32f429xx.s + +DMA1_Stream6_IRQHandler 0000001A + +Symbol: DMA1_Stream6_IRQHandler + Definitions + At line 358 in file startup_stm32f429xx.s + Uses + At line 111 in file startup_stm32f429xx.s + At line 267 in file startup_stm32f429xx.s + +DMA1_Stream7_IRQHandler 0000001A + +Symbol: DMA1_Stream7_IRQHandler + Definitions + At line 388 in file startup_stm32f429xx.s + Uses + At line 141 in file startup_stm32f429xx.s + + + +ARM Macro Assembler Page 4 Alphabetic symbol ordering +Relocatable symbols + + At line 297 in file startup_stm32f429xx.s + +DMA2D_IRQHandler 0000001A + +Symbol: DMA2D_IRQHandler + Definitions + At line 430 in file startup_stm32f429xx.s + Uses + At line 184 in file startup_stm32f429xx.s + At line 339 in file startup_stm32f429xx.s + +DMA2_Stream0_IRQHandler 0000001A + +Symbol: DMA2_Stream0_IRQHandler + Definitions + At line 397 in file startup_stm32f429xx.s + Uses + At line 150 in file startup_stm32f429xx.s + At line 306 in file startup_stm32f429xx.s + +DMA2_Stream1_IRQHandler 0000001A + +Symbol: DMA2_Stream1_IRQHandler + Definitions + At line 398 in file startup_stm32f429xx.s + Uses + At line 151 in file startup_stm32f429xx.s + At line 307 in file startup_stm32f429xx.s + +DMA2_Stream2_IRQHandler 0000001A + +Symbol: DMA2_Stream2_IRQHandler + Definitions + At line 399 in file startup_stm32f429xx.s + Uses + At line 152 in file startup_stm32f429xx.s + At line 308 in file startup_stm32f429xx.s + +DMA2_Stream3_IRQHandler 0000001A + +Symbol: DMA2_Stream3_IRQHandler + Definitions + At line 400 in file startup_stm32f429xx.s + Uses + At line 153 in file startup_stm32f429xx.s + At line 309 in file startup_stm32f429xx.s + +DMA2_Stream4_IRQHandler 0000001A + +Symbol: DMA2_Stream4_IRQHandler + Definitions + At line 401 in file startup_stm32f429xx.s + Uses + At line 154 in file startup_stm32f429xx.s + At line 310 in file startup_stm32f429xx.s + +DMA2_Stream5_IRQHandler 0000001A + +Symbol: DMA2_Stream5_IRQHandler + + + +ARM Macro Assembler Page 5 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 409 in file startup_stm32f429xx.s + Uses + At line 162 in file startup_stm32f429xx.s + At line 318 in file startup_stm32f429xx.s + +DMA2_Stream6_IRQHandler 0000001A + +Symbol: DMA2_Stream6_IRQHandler + Definitions + At line 410 in file startup_stm32f429xx.s + Uses + At line 163 in file startup_stm32f429xx.s + At line 319 in file startup_stm32f429xx.s + +DMA2_Stream7_IRQHandler 0000001A + +Symbol: DMA2_Stream7_IRQHandler + Definitions + At line 411 in file startup_stm32f429xx.s + Uses + At line 164 in file startup_stm32f429xx.s + At line 320 in file startup_stm32f429xx.s + +DebugMon_Handler 00000014 + +Symbol: DebugMon_Handler + Definitions + At line 235 in file startup_stm32f429xx.s + Uses + At line 88 in file startup_stm32f429xx.s + At line 236 in file startup_stm32f429xx.s + +Default_Handler 0000001A + +Symbol: Default_Handler + Definitions + At line 248 in file startup_stm32f429xx.s + Uses + None +Comment: Default_Handler unused +ETH_IRQHandler 0000001A + +Symbol: ETH_IRQHandler + Definitions + At line 402 in file startup_stm32f429xx.s + Uses + At line 155 in file startup_stm32f429xx.s + At line 311 in file startup_stm32f429xx.s + +ETH_WKUP_IRQHandler 0000001A + +Symbol: ETH_WKUP_IRQHandler + Definitions + At line 403 in file startup_stm32f429xx.s + Uses + At line 156 in file startup_stm32f429xx.s + At line 312 in file startup_stm32f429xx.s + + + + +ARM Macro Assembler Page 6 Alphabetic symbol ordering +Relocatable symbols + +EXTI0_IRQHandler 0000001A + +Symbol: EXTI0_IRQHandler + Definitions + At line 347 in file startup_stm32f429xx.s + Uses + At line 100 in file startup_stm32f429xx.s + At line 256 in file startup_stm32f429xx.s + +EXTI15_10_IRQHandler 0000001A + +Symbol: EXTI15_10_IRQHandler + Definitions + At line 381 in file startup_stm32f429xx.s + Uses + At line 134 in file startup_stm32f429xx.s + At line 290 in file startup_stm32f429xx.s + +EXTI1_IRQHandler 0000001A + +Symbol: EXTI1_IRQHandler + Definitions + At line 348 in file startup_stm32f429xx.s + Uses + At line 101 in file startup_stm32f429xx.s + At line 257 in file startup_stm32f429xx.s + +EXTI2_IRQHandler 0000001A + +Symbol: EXTI2_IRQHandler + Definitions + At line 349 in file startup_stm32f429xx.s + Uses + At line 102 in file startup_stm32f429xx.s + At line 258 in file startup_stm32f429xx.s + +EXTI3_IRQHandler 0000001A + +Symbol: EXTI3_IRQHandler + Definitions + At line 350 in file startup_stm32f429xx.s + Uses + At line 103 in file startup_stm32f429xx.s + At line 259 in file startup_stm32f429xx.s + +EXTI4_IRQHandler 0000001A + +Symbol: EXTI4_IRQHandler + Definitions + At line 351 in file startup_stm32f429xx.s + Uses + At line 104 in file startup_stm32f429xx.s + At line 260 in file startup_stm32f429xx.s + +EXTI9_5_IRQHandler 0000001A + +Symbol: EXTI9_5_IRQHandler + Definitions + At line 364 in file startup_stm32f429xx.s + + + +ARM Macro Assembler Page 7 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 117 in file startup_stm32f429xx.s + At line 273 in file startup_stm32f429xx.s + +FLASH_IRQHandler 0000001A + +Symbol: FLASH_IRQHandler + Definitions + At line 345 in file startup_stm32f429xx.s + Uses + At line 98 in file startup_stm32f429xx.s + At line 254 in file startup_stm32f429xx.s + +FMC_IRQHandler 0000001A + +Symbol: FMC_IRQHandler + Definitions + At line 389 in file startup_stm32f429xx.s + Uses + At line 142 in file startup_stm32f429xx.s + At line 298 in file startup_stm32f429xx.s + +FPU_IRQHandler 0000001A + +Symbol: FPU_IRQHandler + Definitions + At line 421 in file startup_stm32f429xx.s + Uses + At line 175 in file startup_stm32f429xx.s + At line 330 in file startup_stm32f429xx.s + +HASH_RNG_IRQHandler 0000001A + +Symbol: HASH_RNG_IRQHandler + Definitions + At line 420 in file startup_stm32f429xx.s + Uses + At line 174 in file startup_stm32f429xx.s + At line 329 in file startup_stm32f429xx.s + +HardFault_Handler 0000000A + +Symbol: HardFault_Handler + Definitions + At line 211 in file startup_stm32f429xx.s + Uses + At line 79 in file startup_stm32f429xx.s + At line 212 in file startup_stm32f429xx.s + +I2C1_ER_IRQHandler 0000001A + +Symbol: I2C1_ER_IRQHandler + Definitions + At line 373 in file startup_stm32f429xx.s + Uses + At line 126 in file startup_stm32f429xx.s + At line 282 in file startup_stm32f429xx.s + +I2C1_EV_IRQHandler 0000001A + + + +ARM Macro Assembler Page 8 Alphabetic symbol ordering +Relocatable symbols + + +Symbol: I2C1_EV_IRQHandler + Definitions + At line 372 in file startup_stm32f429xx.s + Uses + At line 125 in file startup_stm32f429xx.s + At line 281 in file startup_stm32f429xx.s + +I2C2_ER_IRQHandler 0000001A + +Symbol: I2C2_ER_IRQHandler + Definitions + At line 375 in file startup_stm32f429xx.s + Uses + At line 128 in file startup_stm32f429xx.s + At line 284 in file startup_stm32f429xx.s + +I2C2_EV_IRQHandler 0000001A + +Symbol: I2C2_EV_IRQHandler + Definitions + At line 374 in file startup_stm32f429xx.s + Uses + At line 127 in file startup_stm32f429xx.s + At line 283 in file startup_stm32f429xx.s + +I2C3_ER_IRQHandler 0000001A + +Symbol: I2C3_ER_IRQHandler + Definitions + At line 414 in file startup_stm32f429xx.s + Uses + At line 167 in file startup_stm32f429xx.s + At line 323 in file startup_stm32f429xx.s + +I2C3_EV_IRQHandler 0000001A + +Symbol: I2C3_EV_IRQHandler + Definitions + At line 413 in file startup_stm32f429xx.s + Uses + At line 166 in file startup_stm32f429xx.s + At line 322 in file startup_stm32f429xx.s + +LTDC_ER_IRQHandler 0000001A + +Symbol: LTDC_ER_IRQHandler + Definitions + At line 429 in file startup_stm32f429xx.s + Uses + At line 183 in file startup_stm32f429xx.s + At line 338 in file startup_stm32f429xx.s + +LTDC_IRQHandler 0000001A + +Symbol: LTDC_IRQHandler + Definitions + At line 428 in file startup_stm32f429xx.s + Uses + + + +ARM Macro Assembler Page 9 Alphabetic symbol ordering +Relocatable symbols + + At line 182 in file startup_stm32f429xx.s + At line 337 in file startup_stm32f429xx.s + +MemManage_Handler 0000000C + +Symbol: MemManage_Handler + Definitions + At line 216 in file startup_stm32f429xx.s + Uses + At line 80 in file startup_stm32f429xx.s + At line 217 in file startup_stm32f429xx.s + +NMI_Handler 00000008 + +Symbol: NMI_Handler + Definitions + At line 206 in file startup_stm32f429xx.s + Uses + At line 78 in file startup_stm32f429xx.s + At line 207 in file startup_stm32f429xx.s + +OTG_FS_IRQHandler 0000001A + +Symbol: OTG_FS_IRQHandler + Definitions + At line 408 in file startup_stm32f429xx.s + Uses + At line 161 in file startup_stm32f429xx.s + At line 317 in file startup_stm32f429xx.s + +OTG_FS_WKUP_IRQHandler 0000001A + +Symbol: OTG_FS_WKUP_IRQHandler + Definitions + At line 383 in file startup_stm32f429xx.s + Uses + At line 136 in file startup_stm32f429xx.s + At line 292 in file startup_stm32f429xx.s + +OTG_HS_EP1_IN_IRQHandler 0000001A + +Symbol: OTG_HS_EP1_IN_IRQHandler + Definitions + At line 416 in file startup_stm32f429xx.s + Uses + At line 169 in file startup_stm32f429xx.s + At line 325 in file startup_stm32f429xx.s + +OTG_HS_EP1_OUT_IRQHandler 0000001A + +Symbol: OTG_HS_EP1_OUT_IRQHandler + Definitions + At line 415 in file startup_stm32f429xx.s + Uses + At line 168 in file startup_stm32f429xx.s + At line 324 in file startup_stm32f429xx.s + +OTG_HS_IRQHandler 0000001A + + + + +ARM Macro Assembler Page 10 Alphabetic symbol ordering +Relocatable symbols + +Symbol: OTG_HS_IRQHandler + Definitions + At line 418 in file startup_stm32f429xx.s + Uses + At line 171 in file startup_stm32f429xx.s + At line 327 in file startup_stm32f429xx.s + +OTG_HS_WKUP_IRQHandler 0000001A + +Symbol: OTG_HS_WKUP_IRQHandler + Definitions + At line 417 in file startup_stm32f429xx.s + Uses + At line 170 in file startup_stm32f429xx.s + At line 326 in file startup_stm32f429xx.s + +PVD_IRQHandler 0000001A + +Symbol: PVD_IRQHandler + Definitions + At line 342 in file startup_stm32f429xx.s + Uses + At line 95 in file startup_stm32f429xx.s + At line 251 in file startup_stm32f429xx.s + +PendSV_Handler 00000016 + +Symbol: PendSV_Handler + Definitions + At line 239 in file startup_stm32f429xx.s + Uses + At line 90 in file startup_stm32f429xx.s + At line 240 in file startup_stm32f429xx.s + +RCC_IRQHandler 0000001A + +Symbol: RCC_IRQHandler + Definitions + At line 346 in file startup_stm32f429xx.s + Uses + At line 99 in file startup_stm32f429xx.s + At line 255 in file startup_stm32f429xx.s + +RTC_Alarm_IRQHandler 0000001A + +Symbol: RTC_Alarm_IRQHandler + Definitions + At line 382 in file startup_stm32f429xx.s + Uses + At line 135 in file startup_stm32f429xx.s + At line 291 in file startup_stm32f429xx.s + +RTC_WKUP_IRQHandler 0000001A + +Symbol: RTC_WKUP_IRQHandler + Definitions + At line 344 in file startup_stm32f429xx.s + Uses + At line 97 in file startup_stm32f429xx.s + + + +ARM Macro Assembler Page 11 Alphabetic symbol ordering +Relocatable symbols + + At line 253 in file startup_stm32f429xx.s + +Reset_Handler 00000000 + +Symbol: Reset_Handler + Definitions + At line 193 in file startup_stm32f429xx.s + Uses + At line 77 in file startup_stm32f429xx.s + At line 194 in file startup_stm32f429xx.s + +SAI1_IRQHandler 0000001A + +Symbol: SAI1_IRQHandler + Definitions + At line 427 in file startup_stm32f429xx.s + Uses + At line 181 in file startup_stm32f429xx.s + At line 336 in file startup_stm32f429xx.s + +SDIO_IRQHandler 0000001A + +Symbol: SDIO_IRQHandler + Definitions + At line 390 in file startup_stm32f429xx.s + Uses + At line 143 in file startup_stm32f429xx.s + At line 299 in file startup_stm32f429xx.s + +SPI1_IRQHandler 0000001A + +Symbol: SPI1_IRQHandler + Definitions + At line 376 in file startup_stm32f429xx.s + Uses + At line 129 in file startup_stm32f429xx.s + At line 285 in file startup_stm32f429xx.s + +SPI2_IRQHandler 0000001A + +Symbol: SPI2_IRQHandler + Definitions + At line 377 in file startup_stm32f429xx.s + Uses + At line 130 in file startup_stm32f429xx.s + At line 286 in file startup_stm32f429xx.s + +SPI3_IRQHandler 0000001A + +Symbol: SPI3_IRQHandler + Definitions + At line 392 in file startup_stm32f429xx.s + Uses + At line 145 in file startup_stm32f429xx.s + At line 301 in file startup_stm32f429xx.s + +SPI4_IRQHandler 0000001A + +Symbol: SPI4_IRQHandler + + + +ARM Macro Assembler Page 12 Alphabetic symbol ordering +Relocatable symbols + + Definitions + At line 424 in file startup_stm32f429xx.s + Uses + At line 178 in file startup_stm32f429xx.s + At line 333 in file startup_stm32f429xx.s + +SPI5_IRQHandler 0000001A + +Symbol: SPI5_IRQHandler + Definitions + At line 425 in file startup_stm32f429xx.s + Uses + At line 179 in file startup_stm32f429xx.s + At line 334 in file startup_stm32f429xx.s + +SPI6_IRQHandler 0000001A + +Symbol: SPI6_IRQHandler + Definitions + At line 426 in file startup_stm32f429xx.s + Uses + At line 180 in file startup_stm32f429xx.s + At line 335 in file startup_stm32f429xx.s + +SVC_Handler 00000012 + +Symbol: SVC_Handler + Definitions + At line 230 in file startup_stm32f429xx.s + Uses + At line 87 in file startup_stm32f429xx.s + At line 231 in file startup_stm32f429xx.s + +SysTick_Handler 00000018 + +Symbol: SysTick_Handler + Definitions + At line 243 in file startup_stm32f429xx.s + Uses + At line 91 in file startup_stm32f429xx.s + At line 244 in file startup_stm32f429xx.s + +TAMP_STAMP_IRQHandler 0000001A + +Symbol: TAMP_STAMP_IRQHandler + Definitions + At line 343 in file startup_stm32f429xx.s + Uses + At line 96 in file startup_stm32f429xx.s + At line 252 in file startup_stm32f429xx.s + +TIM1_BRK_TIM9_IRQHandler 0000001A + +Symbol: TIM1_BRK_TIM9_IRQHandler + Definitions + At line 365 in file startup_stm32f429xx.s + Uses + At line 118 in file startup_stm32f429xx.s + At line 274 in file startup_stm32f429xx.s + + + +ARM Macro Assembler Page 13 Alphabetic symbol ordering +Relocatable symbols + + +TIM1_CC_IRQHandler 0000001A + +Symbol: TIM1_CC_IRQHandler + Definitions + At line 368 in file startup_stm32f429xx.s + Uses + At line 121 in file startup_stm32f429xx.s + At line 277 in file startup_stm32f429xx.s + +TIM1_TRG_COM_TIM11_IRQHandler 0000001A + +Symbol: TIM1_TRG_COM_TIM11_IRQHandler + Definitions + At line 367 in file startup_stm32f429xx.s + Uses + At line 120 in file startup_stm32f429xx.s + At line 276 in file startup_stm32f429xx.s + +TIM1_UP_TIM10_IRQHandler 0000001A + +Symbol: TIM1_UP_TIM10_IRQHandler + Definitions + At line 366 in file startup_stm32f429xx.s + Uses + At line 119 in file startup_stm32f429xx.s + At line 275 in file startup_stm32f429xx.s + +TIM2_IRQHandler 0000001A + +Symbol: TIM2_IRQHandler + Definitions + At line 369 in file startup_stm32f429xx.s + Uses + At line 122 in file startup_stm32f429xx.s + At line 278 in file startup_stm32f429xx.s + +TIM3_IRQHandler 0000001A + +Symbol: TIM3_IRQHandler + Definitions + At line 370 in file startup_stm32f429xx.s + Uses + At line 123 in file startup_stm32f429xx.s + At line 279 in file startup_stm32f429xx.s + +TIM4_IRQHandler 0000001A + +Symbol: TIM4_IRQHandler + Definitions + At line 371 in file startup_stm32f429xx.s + Uses + At line 124 in file startup_stm32f429xx.s + At line 280 in file startup_stm32f429xx.s + +TIM5_IRQHandler 0000001A + +Symbol: TIM5_IRQHandler + Definitions + + + +ARM Macro Assembler Page 14 Alphabetic symbol ordering +Relocatable symbols + + At line 391 in file startup_stm32f429xx.s + Uses + At line 144 in file startup_stm32f429xx.s + At line 300 in file startup_stm32f429xx.s + +TIM6_DAC_IRQHandler 0000001A + +Symbol: TIM6_DAC_IRQHandler + Definitions + At line 395 in file startup_stm32f429xx.s + Uses + At line 148 in file startup_stm32f429xx.s + At line 304 in file startup_stm32f429xx.s + +TIM7_IRQHandler 0000001A + +Symbol: TIM7_IRQHandler + Definitions + At line 396 in file startup_stm32f429xx.s + Uses + At line 149 in file startup_stm32f429xx.s + At line 305 in file startup_stm32f429xx.s + +TIM8_BRK_TIM12_IRQHandler 0000001A + +Symbol: TIM8_BRK_TIM12_IRQHandler + Definitions + At line 384 in file startup_stm32f429xx.s + Uses + At line 137 in file startup_stm32f429xx.s + At line 293 in file startup_stm32f429xx.s + +TIM8_CC_IRQHandler 0000001A + +Symbol: TIM8_CC_IRQHandler + Definitions + At line 387 in file startup_stm32f429xx.s + Uses + At line 140 in file startup_stm32f429xx.s + At line 296 in file startup_stm32f429xx.s + +TIM8_TRG_COM_TIM14_IRQHandler 0000001A + +Symbol: TIM8_TRG_COM_TIM14_IRQHandler + Definitions + At line 386 in file startup_stm32f429xx.s + Uses + At line 139 in file startup_stm32f429xx.s + At line 295 in file startup_stm32f429xx.s + +TIM8_UP_TIM13_IRQHandler 0000001A + +Symbol: TIM8_UP_TIM13_IRQHandler + Definitions + At line 385 in file startup_stm32f429xx.s + Uses + At line 138 in file startup_stm32f429xx.s + At line 294 in file startup_stm32f429xx.s + + + + +ARM Macro Assembler Page 15 Alphabetic symbol ordering +Relocatable symbols + +UART4_IRQHandler 0000001A + +Symbol: UART4_IRQHandler + Definitions + At line 393 in file startup_stm32f429xx.s + Uses + At line 146 in file startup_stm32f429xx.s + At line 302 in file startup_stm32f429xx.s + +UART5_IRQHandler 0000001A + +Symbol: UART5_IRQHandler + Definitions + At line 394 in file startup_stm32f429xx.s + Uses + At line 147 in file startup_stm32f429xx.s + At line 303 in file startup_stm32f429xx.s + +UART7_IRQHandler 0000001A + +Symbol: UART7_IRQHandler + Definitions + At line 422 in file startup_stm32f429xx.s + Uses + At line 176 in file startup_stm32f429xx.s + At line 331 in file startup_stm32f429xx.s + +UART8_IRQHandler 0000001A + +Symbol: UART8_IRQHandler + Definitions + At line 423 in file startup_stm32f429xx.s + Uses + At line 177 in file startup_stm32f429xx.s + At line 332 in file startup_stm32f429xx.s + +USART1_IRQHandler 0000001A + +Symbol: USART1_IRQHandler + Definitions + At line 378 in file startup_stm32f429xx.s + Uses + At line 131 in file startup_stm32f429xx.s + At line 287 in file startup_stm32f429xx.s + +USART2_IRQHandler 0000001A + +Symbol: USART2_IRQHandler + Definitions + At line 379 in file startup_stm32f429xx.s + Uses + At line 132 in file startup_stm32f429xx.s + At line 288 in file startup_stm32f429xx.s + +USART3_IRQHandler 0000001A + +Symbol: USART3_IRQHandler + Definitions + At line 380 in file startup_stm32f429xx.s + + + +ARM Macro Assembler Page 16 Alphabetic symbol ordering +Relocatable symbols + + Uses + At line 133 in file startup_stm32f429xx.s + At line 289 in file startup_stm32f429xx.s + +USART6_IRQHandler 0000001A + +Symbol: USART6_IRQHandler + Definitions + At line 412 in file startup_stm32f429xx.s + Uses + At line 165 in file startup_stm32f429xx.s + At line 321 in file startup_stm32f429xx.s + +UsageFault_Handler 00000010 + +Symbol: UsageFault_Handler + Definitions + At line 226 in file startup_stm32f429xx.s + Uses + At line 82 in file startup_stm32f429xx.s + At line 227 in file startup_stm32f429xx.s + +WWDG_IRQHandler 0000001A + +Symbol: WWDG_IRQHandler + Definitions + At line 341 in file startup_stm32f429xx.s + Uses + At line 94 in file startup_stm32f429xx.s + At line 250 in file startup_stm32f429xx.s + +102 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +Absolute symbols + +Heap_Size 00000200 + +Symbol: Heap_Size + Definitions + At line 59 in file startup_stm32f429xx.s + Uses + At line 63 in file startup_stm32f429xx.s +Comment: Heap_Size used once +Stack_Size 00000400 + +Symbol: Stack_Size + Definitions + At line 48 in file startup_stm32f429xx.s + Uses + At line 51 in file startup_stm32f429xx.s +Comment: Stack_Size used once +__Vectors_Size 000001AC + +Symbol: __Vectors_Size + Definitions + At line 188 in file startup_stm32f429xx.s + Uses + At line 74 in file startup_stm32f429xx.s +Comment: __Vectors_Size used once +3 symbols + + + +ARM Macro Assembler Page 1 Alphabetic symbol ordering +External symbols + +SystemInit 00000000 + +Symbol: SystemInit + Definitions + At line 195 in file startup_stm32f429xx.s + Uses + At line 198 in file startup_stm32f429xx.s +Comment: SystemInit used once +__main 00000000 + +Symbol: __main + Definitions + At line 196 in file startup_stm32f429xx.s + Uses + At line 200 in file startup_stm32f429xx.s +Comment: __main used once +2 symbols +453 symbols in table diff --git a/MDK-ARM/stm32-keil-unity.uvoptx b/MDK-ARM/stm32-keil-unity.uvoptx index 6346c97..abe303b 100644 --- a/MDK-ARM/stm32-keil-unity.uvoptx +++ b/MDK-ARM/stm32-keil-unity.uvoptx @@ -142,6 +142,9 @@ 1 0 0 + 1 + 0 + 0 11 @@ -200,7 +203,7 @@ 0 0 0 - ../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c + C:\Users\Owner\Desktop\stm32f4-keil-unity\Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c @@ -253,11 +256,19 @@ 0 - - - 0 + 0 + 0 + + + + + + + + 1 + 0 0 2 10000000 @@ -270,7 +281,7 @@ 0x4 ARM-ADS - 168000000 + 12000000 1 1 @@ -322,48 +333,6 @@ 1 18 - - - 0 - STM32F429I-Discovery Quick Start Guide (STM32F429I-Discovery) - C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.9.0\Documentation\32F429IDISCOVERY_QSG.pdf - - - 1 - STM32F429I-Discovery: Blinky Lab (STM32F429I-Discovery) - C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.9.0\Documentation\STMicroelectronics_Blinky_Lab.pdf - - - 2 - Getting Started (STM32F429I-Discovery) - C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.9.0\MDK\Boards\ST\STM32F429I-Discovery\Documentation\DM00092920.pdf - - - 3 - User Manual (STM32F429I-Discovery) - C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.9.0\MDK\Boards\ST\STM32F429I-Discovery\Documentation\DM00093903.pdf - - - 4 - Bill of Materials (STM32F429I-Discovery) - C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.9.0\MDK\Boards\ST\STM32F429I-Discovery\Documentation\stm32f429i-disco_bom.zip - - - 5 - Gerber Files (STM32F429I-Discovery) - C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.9.0\MDK\Boards\ST\STM32F429I-Discovery\Documentation\stm32f429i-disco_gerber.zip - - - 6 - Schematics (STM32F429I-Discovery) - C:\Keil_v5\ARM\PACK\Keil\STM32F4xx_DFP\2.9.0\MDK\Boards\ST\STM32F429I-Discovery\Documentation\stm32f429i-disco_sch.zip - - - 7 - STM32F429I-Discovery Web Page (STM32F429I-Discovery) - http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259090 - - 1 0 @@ -386,7 +355,10 @@ 1 0 0 - 8 + 1 + 0 + 0 + 0 @@ -397,69 +369,41 @@ - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\UL2CM3.DLL 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 + EVENTREC_CNF + -l0 -a1 -s0 -f0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0 - DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F10x_128 -FL020000 -FS08000000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM) 0 - ARMDBGFLAGS - -T0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 0 - UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_2048 -FS08000000 -FL0200000 -FP0($$Device:STM32F429ZITx$CMSIS\Flash\STM32F4xx_2048.FLM)) + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) 0 - ST-LINKIII-KEIL_SWO - -U-O142 -O2254 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32F429ZI$CMSIS\Flash\STM32F4xx_2048.FLM) + ARMDBGFLAGS + -T0 - - - 0 - 0 - 49 - 1 -
134219556
- 0 - 0 - 0 - 0 - 0 - 1 - ..\Test\my_test_Runner.c - - \\stm32_keil_unity\../Test/my_test_Runner.c\49 - - - 1 - 0 - 172 - 1 -
134218312
- 0 - 0 - 0 - 0 - 0 - 1 - ../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c - - \\stm32_keil_unity\../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c\172 - - + + + C:\Users\Owner\AppData\Local\Arm\Packs\Keil\ARM_Compiler\1.6.2\EventRecorder.scvd + Keil.ARM_Compiler.1.6.2 + 1 + 0 @@ -492,11 +436,19 @@ 0 - - - 0 + 0 + 0 + + + + + + + + 1 + 1 0 2 10000000 @@ -505,7 +457,7 @@ - Drivers/CMSIS + Application/User 0 0 0 @@ -517,238 +469,6 @@ 0 0 0 - ../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c - system_stm32f4xx.c - 0 - 0 - - - - - Drivers/STM32F4xx_HAL_Driver - 0 - 0 - 0 - 0 - - 2 - 2 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c - stm32f4xx_hal_dma_ex.c - 0 - 0 - - - 2 - 3 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c - stm32f4xx_hal_gpio.c - 0 - 0 - - - 2 - 4 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c - stm32f4xx_hal.c - 0 - 0 - - - 2 - 5 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c - stm32f4xx_hal_rcc.c - 0 - 0 - - - 2 - 6 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c - stm32f4xx_hal_flash_ex.c - 0 - 0 - - - 2 - 7 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c - stm32f4xx_hal_dma.c - 0 - 0 - - - 2 - 8 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c - stm32f4xx_hal_pwr.c - 0 - 0 - - - 2 - 9 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c - stm32f4xx_hal_tim_ex.c - 0 - 0 - - - 2 - 10 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c - stm32f4xx_hal_flash.c - 0 - 0 - - - 2 - 11 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c - stm32f4xx_hal_cortex.c - 0 - 0 - - - 2 - 12 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c - stm32f4xx_hal_rcc_ex.c - 0 - 0 - - - 2 - 13 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c - stm32f4xx_hal_pwr_ex.c - 0 - 0 - - - 2 - 14 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c - stm32f4xx_hal_tim.c - 0 - 0 - - - 2 - 15 - 1 - 0 - 0 - 0 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c - stm32f4xx_hal_flash_ramfunc.c - 0 - 0 - - - - - Application/User - 1 - 0 - 0 - 0 - - 3 - 16 - 1 - 0 - 0 - 0 - ../Src/stm32f4xx_it.c - stm32f4xx_it.c - 0 - 0 - - - 3 - 17 - 1 - 0 - 0 - 0 - ../Src/gpio.c - gpio.c - 0 - 0 - - - 3 - 18 - 1 - 0 - 0 - 0 - ../Src/stm32f4xx_hal_msp.c - stm32f4xx_hal_msp.c - 0 - 0 - - - 3 - 19 - 1 - 0 - 0 - 0 ../Src/main.c main.c 0 @@ -762,18 +482,6 @@ 0 0 0 - - 4 - 20 - 2 - 0 - 0 - 0 - startup_stm32f429xx.s - startup_stm32f429xx.s - 0 - 0 - @@ -783,8 +491,8 @@ 0 0 - 5 - 21 + 3 + 2 1 1 0 @@ -803,8 +511,8 @@ 0 0 - 6 - 22 + 4 + 3 1 0 0 @@ -815,8 +523,8 @@ 0 - 6 - 23 + 4 + 4 1 0 0 @@ -834,18 +542,6 @@ 0 0 0 - - 7 - 24 - 1 - 0 - 0 - 0 - ..\Usr\debug_printf.c - debug_printf.c - 0 - 0 - @@ -856,4 +552,20 @@ 1 + + ::Compiler + 1 + 0 + 0 + 1 + + + + ::Device + 1 + 0 + 0 + 1 + + diff --git a/MDK-ARM/stm32-keil-unity.uvprojx b/MDK-ARM/stm32-keil-unity.uvprojx index 693acbc..d23b321 100644 --- a/MDK-ARM/stm32-keil-unity.uvprojx +++ b/MDK-ARM/stm32-keil-unity.uvprojx @@ -11,12 +11,13 @@ 0x4 ARM-ADS 5060183::V5.06 update 2 (build 183)::ARMCC + 0 STM32F429ZITx STMicroelectronics - Keil.STM32F4xx_DFP.2.9.0 - http://www.keil.com/pack + Keil.STM32F4xx_DFP.2.14.0 + http://www.keil.com/pack/ IRAM(0x20000000-0x2002FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 @@ -183,6 +184,7 @@ 0 0 2 + 0 1 0 8 @@ -323,6 +325,7 @@ 0 0 0 + 0 0 1 1 @@ -330,6 +333,7 @@ 1 0 0 + 0 --C99 USE_HAL_DRIVER,STM32F429xx @@ -347,6 +351,7 @@ 0 0 0 + 0 @@ -374,109 +379,9 @@ - - Drivers/CMSIS - - - system_stm32f4xx.c - 1 - ../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c - - - - - Drivers/STM32F4xx_HAL_Driver - - - stm32f4xx_hal_dma_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c - - - stm32f4xx_hal_gpio.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c - - - stm32f4xx_hal.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c - - - stm32f4xx_hal_rcc.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c - - - stm32f4xx_hal_flash_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c - - - stm32f4xx_hal_dma.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c - - - stm32f4xx_hal_pwr.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c - - - stm32f4xx_hal_tim_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c - - - stm32f4xx_hal_flash.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c - - - stm32f4xx_hal_cortex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c - - - stm32f4xx_hal_rcc_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c - - - stm32f4xx_hal_pwr_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c - - - stm32f4xx_hal_tim.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c - - - stm32f4xx_hal_flash_ramfunc.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c - - - Application/User - - stm32f4xx_it.c - 1 - ../Src/stm32f4xx_it.c - - - gpio.c - 1 - ../Src/gpio.c - - - stm32f4xx_hal_msp.c - 1 - ../Src/stm32f4xx_hal_msp.c - main.c 1 @@ -486,13 +391,6 @@ Application/MDK-ARM - - - startup_stm32f429xx.s - 2 - startup_stm32f429xx.s - - Lib/Unity @@ -529,6 +427,7 @@ 2 2 2 + 2 2 0 0 @@ -536,6 +435,7 @@ 2 0 0 + 2 @@ -553,6 +453,7 @@ 2 2 2 + 2 @@ -600,6 +501,7 @@ 2 2 2 + 2 2 0 0 @@ -607,6 +509,7 @@ 2 0 0 + 2 @@ -654,6 +557,7 @@ 2 2 2 + 2 2 0 0 @@ -661,6 +565,7 @@ 2 0 0 + 2 @@ -678,6 +583,7 @@ 2 2 2 + 2 @@ -725,6 +631,7 @@ 2 2 2 + 2 2 0 0 @@ -732,6 +639,7 @@ 2 0 0 + 2 @@ -751,85 +659,105 @@ Usr - - - debug_printf.c - 1 - ..\Usr\debug_printf.c - - - 2 - 0 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 0 - 0 - - - - - - - - - - - ::CMSIS + + ::Compiler + + + ::Device + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + Test 0x4 ARM-ADS - 5060183::V5.06 update 2 (build 183)::ARMCC + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 - STM32F429ZITx + STM32F103RB STMicroelectronics - Keil.STM32F4xx_DFP.2.9.0 - http://www.keil.com/pack - IRAM(0x20000000-0x2002FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x81FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 + Keil.STM32F1xx_DFP.2.3.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00005000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE - - - + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)) + 4231 + $$Device:STM32F103RB$Device\Include\stm32f10x.h @@ -839,7 +767,7 @@ - $$Device:STM32F429ZITx$CMSIS\SVD\STM32F429x.svd + $$Device:STM32F103RB$SVD\STM32F103xx.svd 0 0 @@ -876,9 +804,9 @@ 0 - 1 + 0 0 - D:\Ruby23\bin\ruby.exe ..\Lib\unity\auto\generate_test_runner.rb ..\\Test\\my_test.c + C:\Ruby26-x64\bin\ruby.exe ..\Lib\unity\auto\generate_test_runner.rb ..\\Test\\my_test.c 0 0 @@ -916,13 +844,13 @@ SARMCM3.DLL - -REMAP -MPU - DCM.DLL - -pCM4 + + DARMSTM.DLL + -pSTM32F103RB SARMCM3.DLL - -MPU - TCM.DLL - -pCM4 + + TARMSTM.DLL + -pSTM32F103RB @@ -943,7 +871,7 @@ 4107 1 - STLink\ST-LINKIII-KEIL_SWO.dll + BIN\UL2CM3.DLL @@ -980,7 +908,7 @@ 1 0 0 - "Cortex-M4" + "Cortex-M3" 0 0 @@ -989,8 +917,9 @@ 1 0 0 - 2 - 1 + 0 + 0 + 0 0 8 1 @@ -1050,12 +979,12 @@ 0 0x20000000 - 0x30000 + 0x5000 1 0x8000000 - 0x200000 + 0x20000 0 @@ -1080,7 +1009,7 @@ 1 0x8000000 - 0x200000 + 0x20000 1 @@ -1105,12 +1034,12 @@ 0 0x20000000 - 0x30000 + 0x5000 0 - 0x10000000 - 0x10000 + 0x0 + 0x0 @@ -1130,6 +1059,7 @@ 0 0 1 + 0 0 1 1 @@ -1137,6 +1067,7 @@ 1 0 0 + 0 USE_HAL_DRIVER,STM32F429xx @@ -1154,6 +1085,7 @@ 0 0 0 + 0 @@ -1181,223 +1113,6 @@ - - Drivers/CMSIS - - - 0 - 0 - 0 - 0 - 0 - 1 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 0 - 0 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - - system_stm32f4xx.c - 1 - ../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c - - - - - Drivers/STM32F4xx_HAL_Driver - - - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 0 - 0 - - - - - - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - - - - stm32f4xx_hal_dma_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c - - - stm32f4xx_hal_gpio.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c - - - stm32f4xx_hal.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c - - - stm32f4xx_hal_rcc.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c - - - stm32f4xx_hal_flash_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c - - - stm32f4xx_hal_dma.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c - - - stm32f4xx_hal_pwr.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c - - - stm32f4xx_hal_tim_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c - - - stm32f4xx_hal_flash.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c - - - stm32f4xx_hal_cortex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c - - - stm32f4xx_hal_rcc_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c - - - stm32f4xx_hal_pwr_ex.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c - - - stm32f4xx_hal_tim.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c - - - stm32f4xx_hal_flash_ramfunc.c - 1 - ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c - - - Application/User @@ -1433,6 +1148,7 @@ 2 2 2 + 2 2 0 0 @@ -1440,6 +1156,7 @@ 2 0 0 + 2 @@ -1457,6 +1174,7 @@ 2 2 2 + 2 @@ -1467,21 +1185,6 @@ - - stm32f4xx_it.c - 1 - ../Src/stm32f4xx_it.c - - - gpio.c - 1 - ../Src/gpio.c - - - stm32f4xx_hal_msp.c - 1 - ../Src/stm32f4xx_hal_msp.c - main.c 1 @@ -1524,6 +1227,7 @@ 2 2 2 + 2 2 0 0 @@ -1531,6 +1235,7 @@ 2 0 0 + 2 @@ -1548,6 +1253,7 @@ 2 2 2 + 2 @@ -1557,13 +1263,6 @@ - - - startup_stm32f429xx.s - 2 - startup_stm32f429xx.s - - Lib/Unity @@ -1592,17 +1291,16 @@ Usr - - - debug_printf.c - 1 - ..\Usr\debug_printf.c - - ::CMSIS + + ::Compiler + + + ::Device + @@ -1610,15 +1308,91 @@ - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + RTE\Compiler\EventRecorderConf.h + + + + + + + + + RTE\Device\STM32F103RB\RTE_Device.h + + + + + + + + RTE\Device\STM32F103RB\startup_stm32f10x_md.s + + + + + + + + RTE\Device\STM32F103RB\system_stm32f10x.c + + + + + + + + RTE\Device\STM32F429ZITx\startup_stm32f429xx.s + + + + + + + + RTE\Device\STM32F429ZITx\system_stm32f4xx.c + + + + + + + diff --git a/Test/my_test.c b/Test/my_test.c index 96d7103..99b1ea0 100644 --- a/Test/my_test.c +++ b/Test/my_test.c @@ -3,17 +3,17 @@ #include "debug_printf.h" void setUp() { - printf("setUp my_test\n"); + //printf("setUp my_test\n"); } void tearDown() { - printf("tearDown my_test\n"); + //printf("tearDown my_test\n"); } void testWillAlwaysPass(void) { TEST_ASSERT_EQUAL_INT(42,42); } -void xxtestWillAlwaysFail(void) { +void testWillAlwaysFail(void) { TEST_ASSERT_EQUAL_INT(42,1); } diff --git a/Test/my_test_Runner.c b/Test/my_test_Runner.c index 1dbe99c..37d5fb8 100644 --- a/Test/my_test_Runner.c +++ b/Test/my_test_Runner.c @@ -22,12 +22,13 @@ #include "unity.h" #include #include -#include "debug_printf.h" - +//#include "debug_printf.h" +#include "EventRecorder.h" /*=======External Functions This Runner Calls=====*/ extern void setUp(void); extern void tearDown(void); extern void testWillAlwaysPass(void); +extern void testWillAlwaysFail(void); /*=======Test Reset Option=====*/ @@ -42,8 +43,11 @@ void resetTest(void) /*=======MAIN=====*/ int main(void) { + EventRecorderInitialize(EventRecordAll, 1); UnityBegin("..\\Test\\my_test.c"); RUN_TEST(testWillAlwaysPass, 13); + RUN_TEST(testWillAlwaysFail, 17); + UnityEnd(); - return (UnityEnd()); + while(1); } diff --git a/stm32-keil-unity.ioc b/stm32-keil-unity.ioc index 3ed2d2a..4b98587 100644 --- a/stm32-keil-unity.ioc +++ b/stm32-keil-unity.ioc @@ -15,33 +15,26 @@ Mcu.Pin3=PG13 Mcu.Pin4=PG14 Mcu.Pin5=VP_SYS_VS_Systick Mcu.PinsNb=6 +Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F429ZITx MxCube.Version=4.15.0 MxDb.Version=DB.4.0.150 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false PA0/WKUP.GPIOParameters=GPIO_Label PA0/WKUP.GPIO_Label=BTN_USER PA0/WKUP.Locked=true PA0/WKUP.Signal=GPIO_Input -PCC.Checker=false -PCC.Line=STM32F429/439 -PCC.MCU=STM32F429Z(E-G-I)Tx -PCC.MXVersion=4.15.0 -PCC.PartNumber=STM32F429ZITx -PCC.Seq0=0 -PCC.Series=STM32F4 -PCC.Temperature=25 -PCC.Vdd=null PG13.GPIOParameters=GPIO_Label PG13.GPIO_Label=LED_GREEN PG13.Locked=true @@ -54,11 +47,14 @@ PH0/OSC_IN.Mode=HSE-External-Oscillator PH0/OSC_IN.Signal=RCC_OSC_IN PH1/OSC_OUT.Mode=HSE-External-Oscillator PH1/OSC_OUT.Signal=RCC_OSC_OUT -ProjectManager.AskForMigrate=true +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=false ProjectManager.BackupPrevious=false ProjectManager.CompilerOptimize=2 ProjectManager.ComputerToolchain=false ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F429ZITx ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.12.0 @@ -68,15 +64,17 @@ ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true ProjectManager.LastFirmware=true ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Src +ProjectManager.NoMain=false ProjectManager.PreviousToolchain= ProjectManager.ProjectBuild=false ProjectManager.ProjectFileName=stm32-keil-unity.ioc ProjectManager.ProjectName=stm32-keil-unity ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=MDK-ARM V5 -ProjectManager.ToolChainLocation=D\:\\projects\\stm32-keil-unity +ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false +ProjectManager.functionlistsort= RCC.48MHZClocksFreq_Value=84000000 RCC.AHBFreq_Value=168000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4