Create a primitive for initialized async RAM

[LithosphereRocketry]

Re: discussion in https://clash-lang.discourse.group/t/initializing-one-word-of-asyncram/94

Many FPGA architectures allow async RAM primitives to have initial values while still being writable. In previous designs I've found that in my particular case (ECP5 with Yosys/NextPNR) using a distributed RAM block with an initializer is the fastest way to implement structures like a RISCV register file with a zero register (compared to multiplexing a 0 into the output or having the whole thing fall back to DFF registers.)

It would be nice to have a variant of the asyncRam primitive that allows the contents to be initalized similar to asyncRom. Notably the blockRam primitive already supports this so it would be nice for it to align with that as much as is reasonable.