Incorrect reference to ARM architecture

[raulbehl]

The README for LAB 3 and 4 says:

LAB 3 - "This lab consists of verilog code for a single cycle implementation for ARM architecture with the following limited instruction set:"

LAB 4 - "Basic Pipelined ARM Architecture implementation"

As it says it is a "single cycle implementation for ARM architecture" or a "Basic Pipelined ARM Architecture implementation" but the instructions loaded onto instruction memory resemble MIPS ISA. Also the instruction encoding do not match any of the THUMB (16-bit) variants. There are no lw, sw, addi, subi, instructions in any of the ARM ISA. Also the register are directly referenced as R0..R31 in all ARM instructions and not as $r0..$r31. The way instructions are decoded and register are referenced, it clearly resembles a MIPS architecture.
I think the two README files should be updated to reflect the same.

[bhavul]

Hey Rahul. Thanks for notifying of the issue. I am quite out of touch with
Computer Architecture and verilog though. If you're updated with what the
issue is, and know the correction, could you go ahead and open a pull
request for the same?

ᐧ

On 7 December 2015 at 12:17, Rahul Behl notifications@github.com wrote:

The README for LAB 3 and 4 says:

LAB 3 - "This lab consists of verilog code for a single cycle
implementation for ARM architecture with the following limited instruction
set:"

LAB 4 - "Basic Pipelined ARM Architecture implementation"

As it says it is a "single cycle implementation for ARM architecture" or a
"Basic Pipelined ARM Architecture implementation" but the instructions
loaded onto instruction memory resemble MIPS ISA. Also the instruction
encoding do not match any of the THUMB (16-bit) variants. There are no lw,
sw, addi, subi, instructions in any of the ARM ISA. Also the register are
directly referenced as R0..R31 in all ARM instructions and not as
$r0..$r31. The way instructions are decoded and register are referenced, it
clearly resembles a MIPS architecture.
I think the two README files should be updated to reflect the same.

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Bhavul Gauri
Student
Msc.(Hons.) Mathematics
B.E.(Hons.) Computer Science and Engineering

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