From 095d4a577d121a8f32cd7a8c005984be968eed38 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Mon, 22 Sep 2025 15:04:59 +0300 Subject: [PATCH 01/10] cn0577_adaq2387x: Update tb to work for cn0577 & adaq2387x Signed-off-by: Stanca Pop --- testbenches/project/cn0577_adaq2387x/Makefile | 42 ++ .../project/cn0577_adaq2387x/README.md | 27 ++ .../cfgs/cfg_adaq2387x_1lane_16b.tcl | 6 + .../cfgs/cfg_adaq2387x_1lane_18b.tcl | 6 + .../cfgs/cfg_adaq2387x_2lanes_16b.tcl | 6 + .../cfgs/cfg_adaq2387x_2lanes_18b.tcl | 6 + .../cfgs/cfg_cn0577_1lane.tcl | 6 + .../cfgs/cfg_cn0577_2lanes.tcl | 6 + .../project/cn0577_adaq2387x/system_bd.tcl | 68 +++ .../cn0577_adaq2387x/system_project.tcl | 42 ++ .../project/cn0577_adaq2387x/system_tb.sv | 115 +++++ .../cn0577_adaq2387x/tests/test_program.sv | 426 ++++++++++++++++++ .../waves/system_tb_behav.wcfg | 160 +++++++ 13 files changed, 916 insertions(+) create mode 100644 testbenches/project/cn0577_adaq2387x/Makefile create mode 100644 testbenches/project/cn0577_adaq2387x/README.md create mode 100644 testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_16b.tcl create mode 100644 testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_18b.tcl create mode 100644 testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_16b.tcl create mode 100644 testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_18b.tcl create mode 100644 testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_1lane.tcl create mode 100644 testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_2lanes.tcl create mode 100644 testbenches/project/cn0577_adaq2387x/system_bd.tcl create mode 100644 testbenches/project/cn0577_adaq2387x/system_project.tcl create mode 100644 testbenches/project/cn0577_adaq2387x/system_tb.sv create mode 100644 testbenches/project/cn0577_adaq2387x/tests/test_program.sv create mode 100644 testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg diff --git a/testbenches/project/cn0577_adaq2387x/Makefile b/testbenches/project/cn0577_adaq2387x/Makefile new file mode 100644 index 000000000..f540dda5f --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/Makefile @@ -0,0 +1,42 @@ +#################################################################################### +#################################################################################### +## Copyright (C) 2025 Analog Devices, Inc. +#################################################################################### +#################################################################################### + +# Makeincludes +include ../../../scripts/make_tb_path.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_dmac.mk +include $(TB_LIBRARY_PATH)/includes/Makeinclude_converter.mk + +# Remaining test-bench dependencies except test programs + +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_ltc2387 + +# default test programs +# Format is: +TP := $(notdir $(basename $(wildcard tests/*.sv))) + +# config files should have the following format +# cfg__.tcl +CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) + +# List of tests and configuration combinations that has to be run +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP))) + +include $(ADI_TB_DIR)/scripts/project-sim.mk + +# usage : +# +# run specific test on a specific configuration in gui mode +# make CFG=cfg1 TST=test_program MODE=gui +# +# run all test from a configuration +# make cfg1 + +#################################################################################### +#################################################################################### diff --git a/testbenches/project/cn0577_adaq2387x/README.md b/testbenches/project/cn0577_adaq2387x/README.md new file mode 100644 index 000000000..f1495cb4e --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/README.md @@ -0,0 +1,27 @@ +Usage : + +Run all tests in batch mode: + + make + + +Run all tests in GUI mode: + + make MODE=gui + + +Run specific test on a specific configuration in gui mode: + + make CFG= TST= MODE=gui + + +Run all test from a configuration: + + make + + +Where: + + * is a file from the cfgs directory without the tcl extension of format cfg\* + * is a file from the tests directory without the tcl extension + diff --git a/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_16b.tcl b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_16b.tcl new file mode 100644 index 000000000..6bdafc394 --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_16b.tcl @@ -0,0 +1,6 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 0 +set ad_project_params(ADC_RES) 16 +set ad_project_params(CN0577_ADAQ2387X_N) 0 +set ad_project_params(USE_MMCM) 0 diff --git a/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_18b.tcl b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_18b.tcl new file mode 100644 index 000000000..b90234ac0 --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_1lane_18b.tcl @@ -0,0 +1,6 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 0 +set ad_project_params(ADC_RES) 18 +set ad_project_params(CN0577_ADAQ2387X_N) 0 +set ad_project_params(USE_MMCM) 0 diff --git a/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_16b.tcl b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_16b.tcl new file mode 100644 index 000000000..f999516cf --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_16b.tcl @@ -0,0 +1,6 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 1 +set ad_project_params(ADC_RES) 16 +set ad_project_params(CN0577_ADAQ2387X_N) 0 +set ad_project_params(USE_MMCM) 0 diff --git a/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_18b.tcl b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_18b.tcl new file mode 100644 index 000000000..e91977ef0 --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_adaq2387x_2lanes_18b.tcl @@ -0,0 +1,6 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 1 +set ad_project_params(ADC_RES) 18 +set ad_project_params(CN0577_ADAQ2387X_N) 0 +set ad_project_params(USE_MMCM) 0 diff --git a/testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_1lane.tcl b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_1lane.tcl new file mode 100644 index 000000000..9757998da --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_1lane.tcl @@ -0,0 +1,6 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 0 +set ad_project_params(ADC_RES) 18 +set ad_project_params(CN0577_ADAQ2387X_N) 1 +set ad_project_params(USE_MMCM) 0 diff --git a/testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_2lanes.tcl b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_2lanes.tcl new file mode 100644 index 000000000..f7b2718a9 --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/cfgs/cfg_cn0577_2lanes.tcl @@ -0,0 +1,6 @@ +global ad_project_params + +set ad_project_params(TWOLANES) 1 +set ad_project_params(ADC_RES) 18 +set ad_project_params(CN0577_ADAQ2387X_N) 1 +set ad_project_params(USE_MMCM) 0 diff --git a/testbenches/project/cn0577_adaq2387x/system_bd.tcl b/testbenches/project/cn0577_adaq2387x/system_bd.tcl new file mode 100644 index 000000000..1233d0160 --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/system_bd.tcl @@ -0,0 +1,68 @@ +# *************************************************************************** +# *************************************************************************** +# Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +# +# In this HDL repository, there are many different and unique modules, consisting +# of various HDL (Verilog or VHDL) components. The individual modules are +# developed independently, and may be accompanied by separate and unique license +# terms. +# +# The user should read each of these license terms, and understand the +# freedoms and responsibilities that he or she has by using this source/core. +# +# This core is distributed in the hope that it will be useful, but WITHOUT ANY +# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +# A PARTICULAR PURPOSE. +# +# Redistribution and use of source or resulting binaries, with or without modification +# of this file, are permitted under one of the following two license terms: +# +# 1. The GNU General Public License version 2 as published by the +# Free Software Foundation, which can be found in the top level directory +# of this repository (LICENSE_GPL2), and also online at: +# +# +# OR +# +# 2. An ADI specific BSD license, which can be found in the top level directory +# of this repository (LICENSE_ADIBSD), and also on-line at: +# https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +# This will allow to generate bit files and not release the source code, +# as long as it attaches to an ADI device. +# +# *************************************************************************** +# *************************************************************************** + +global ad_project_params + +# system level parameters +set TWOLANES $ad_project_params(TWOLANES) +set ADC_RES $ad_project_params(ADC_RES) +set CN0577_ADAQ2387X_N $ad_project_params(CN0577_ADAQ2387X_N) +set USE_MMCM $ad_project_params(USE_MMCM) + +adi_project_files [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ +] + +# +# Block design under test +# + +if {$CN0577_ADAQ2387X_N == 1} { + source $ad_hdl_dir/projects/cn0577/common/cn0577_bd.tcl +} else { + source $ad_hdl_dir/projects/adaq2387x/common/adaq2387x_bd.tcl +} + +set BA_AXI_LTC2387 0x44A00000 +set_property offset $BA_AXI_LTC2387 [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387}] +adi_sim_add_define "AXI_LTC2387_BA=[format "%d" ${BA_AXI_LTC2387}]" + +set BA_DMA 0x44A30000 +set_property offset $BA_DMA [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387_dma}] +adi_sim_add_define "AXI_LTC2387_DMA_BA=[format "%d" ${BA_DMA}]" + +set BA_PWM 0x44A60000 +set_property offset $BA_PWM [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_pwm_gen}] +adi_sim_add_define "AXI_PWM_GEN_BA=[format "%d" ${BA_PWM}]" diff --git a/testbenches/project/cn0577_adaq2387x/system_project.tcl b/testbenches/project/cn0577_adaq2387x/system_project.tcl new file mode 100644 index 000000000..dcb396df4 --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/system_project.tcl @@ -0,0 +1,42 @@ +source ../../../scripts/adi_sim.tcl + +if {$argc < 1} { + puts "Expecting at least one argument that specifies the test configuration" + exit 1 +} else { + set cfg_file [lindex $argv 0] +} + +# Read common config file +source "cfgs/${cfg_file}" + +# Set the project name +set project_name [file rootname $cfg_file] + +# Set project params +global ad_project_params + +set TWOLANES $ad_project_params(TWOLANES) +set ADC_RES $ad_project_params(ADC_RES) +set CN0577_ADAQ2387X_N $ad_project_params(CN0577_ADAQ2387X_N) +set USE_MMCM $ad_project_params(USE_MMCM) + +# Set to use SmartConnect or AXI Interconnect +set use_smartconnect 1 + +# Create the project +adi_sim_project_xilinx $project_name "xc7z007sclg400-1" + +source $ad_tb_dir/library/includes/sp_include_dmac.tcl +source $ad_tb_dir/library/includes/sp_include_pwm_gen.tcl +source $ad_tb_dir/library/includes/sp_include_converter.tcl + +# Add test files to the project +adi_sim_project_files [list \ + "tests/test_program.sv" +] + +#set a default test program +adi_sim_add_define "TEST_PROGRAM=test_program" + +adi_sim_generate $project_name diff --git a/testbenches/project/cn0577_adaq2387x/system_tb.sv b/testbenches/project/cn0577_adaq2387x/system_tb.sv new file mode 100644 index 000000000..e9a1ee4ca --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/system_tb.sv @@ -0,0 +1,115 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +`include "utils.svh" + +module system_tb(); + + // dco delay compared to the reference clk + localparam DCO_DELAY = 12; + + // reg signals + + reg ref_clk = 1'b0; + reg dco_init = 1'b0; + reg cnv_out = 1'b0; + reg clk_gate = 1'b0; + reg dco_p; + reg dco_n; + reg da_p = 1'b0; + reg da_n = 1'b0; + reg db_p = 1'b0; + reg db_n = 1'b0; + + // dma interface + + wire adc_valid; + wire [`ADC_RES-1:0] adc_data; + reg adc_dovf = 1'b0; + + wire cnv; + reg dco = 1'b0; + + integer cnv_count = 0; + + // test bench variables + + always #25 ref_clk = ~ref_clk; + + // --------------------------------------------------------------------------- + // Creating a "gate" through which the data clock can run (and only then) + // --------------------------------------------------------------------------- + always @ (*) begin + if (clk_gate == 1'b1) begin + dco_init = ref_clk; + end else begin + dco_init = 1'b0; + end + end + + // Data clocks generation + // --------------------------------------------------------------------------- + + always @ (dco_init) begin + dco_p <= #DCO_DELAY dco_init; + dco_n <= #DCO_DELAY ~dco_init; + end + + `TEST_PROGRAM test( + .ref_clk (ref_clk), + .clk_gate (clk_gate), + .dco_in (dco_init), + .da_p (da_p), + .da_n (da_n), + .db_p (db_p), + .db_n (db_n), + .cnv (cnv)); + + test_harness `TH ( + .ref_clk (ref_clk), + .sampling_clk (sampling_clk), + .dco_p (dco_p), + .dco_n (dco_n), + .cnv (cnv), + .da_n (da_n), + .da_p (da_p), + .db_n (db_n), + .db_p (db_p), + .clk_gate (clk_gate)); + +endmodule + diff --git a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv new file mode 100644 index 000000000..0e2b1a160 --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv @@ -0,0 +1,426 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`include "utils.svh" + +import axi_vip_pkg::*; +import axi4stream_vip_pkg::*; +import logger_pkg::*; +import test_harness_env_pkg::*; +import dmac_api_pkg::*; +import adc_api_pkg::*; +import pwm_gen_api_pkg::*; +import common_api_pkg::*; + +import `PKGIFY(test_harness, mng_axi_vip)::*; +import `PKGIFY(test_harness, ddr_axi_vip)::*; + +localparam NUM_OF_TRANSFERS = 16; + +//--------------------------------------------------------------------------- +// SPI Engine configuration parameters +//--------------------------------------------------------------------------- + +program test_program ( + input ref_clk, + input clk_gate, + input dco_in, + output da_n, + output da_p, + output db_n, + output db_p, + output reg dco_p, + output reg dco_n, + input cnv); + +timeunit 1ns; +timeprecision 1ps; + +typedef enum {DATA_MODE_RANDOM, DATA_MODE_RAMP, DATA_MODE_PATTERN} offload_test_t; + +test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; + +// set to active debug messages +localparam bit DEBUG = 1; + +// dco delay compared to the reference clk +localparam DCO_DELAY = 12; + +dmac_api cn0577_dmac_api; +pwm_gen_api cn0577_pwm_gen_api; +adc_api ltc2387_adc_api; +common_api ltc2387_common_api; + +// dma interface +wire adc_valid; +wire [`ADC_RES-1:0] adc_data; +reg adc_dovf = 1'b0; + +// -------------------------- +// Main procedure +// -------------------------- + +initial begin + + //creating environment + base_env = new("Base Environment", + `TH.`SYS_CLK.inst.IF, + `TH.`DMA_CLK.inst.IF, + `TH.`DDR_CLK.inst.IF, + `TH.`SYS_RST.inst.IF, + `TH.`MNG_AXI.inst.IF, + `TH.`DDR_AXI.inst.IF); + cn0577_dmac_api = new( + "CN0577 DMAC API", + base_env.mng.sequencer, + `AXI_LTC2387_DMA_BA); + + cn0577_pwm_gen_api = new( + "CN0577 AXI PWM GEN API", + base_env.mng.sequencer, + `AXI_PWM_GEN_BA); + + ltc2387_adc_api = new( + "LTC2387 ADC Common API", + base_env.mng.sequencer, + `AXI_LTC2387_BA); + + ltc2387_common_api = new( + "LTC2387 Common API", + base_env.mng.sequencer, + `AXI_LTC2387_BA); + + base_env.start(); + base_env.sys_reset(); + + sanity_tests(); + + #100ns; + + data_acquisition_test(); + + base_env.stop(); + + `INFO(("Test Done"), ADI_VERBOSITY_NONE); + $finish(); + +end + +bit [31:0] dma_data_store_arr [(NUM_OF_TRANSFERS) - 1:0]; +bit transfer_status = 0; +bit [31:0] transfer_cnt; + +//--------------------------------------------------------------------------- +// Transfer Counter +//--------------------------------------------------------------------------- + +initial begin + transfer_cnt = 0; + forever begin + @(posedge cnv); + if (transfer_status) begin + transfer_cnt = transfer_cnt + 1; + end + @(negedge cnv); + end +end + +//--------------------------------------------------------------------------- +// Clk_gate shifted copy +//--------------------------------------------------------------------------- + +localparam int N = (`TWOLANES == 0 && `ADC_RES == 16) ? 16 : + (`TWOLANES == 0 && `ADC_RES == 18) ? 18 : + (`TWOLANES == 1 && `ADC_RES == 16) ? 8 : + (`TWOLANES == 1 && `ADC_RES == 18) ? 10 : + -1; // Error case +parameter int num_of_dco = N / 2; + +initial begin + forever begin + @(posedge dco_in, negedge dco_in) begin + #1 + dco_p <= dco_in; + dco_n <= ~dco_in; + end + end + end + +//--------------------------------------------------------------------------- +// Data store +//--------------------------------------------------------------------------- + +reg [`ADC_RES-1:0] data_gen = 'h3a5a5; +reg [`ADC_RES-1:0] data_shift = 'h0; + +reg r_da_p = 1'b0; +reg r_da_n = 1'b0; +reg r_db_p = 1'b0; +reg r_db_n = 1'b0; + +assign da_p = r_da_p; +assign da_n = r_da_n; +assign db_p = r_db_p; +assign db_n = r_db_n; + +// --------------------------------------------------------------------------- +// Output data ready +// --------------------------------------------------------------------------- + +initial begin + forever begin + @ (posedge dco_in, negedge dco_in) begin + if (`TWOLANES == 1) begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + r_db_p = data_shift[`ADC_RES - 2]; + r_db_n = ~data_shift[`ADC_RES - 2]; + data_shift = data_shift << 2; + end else begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + data_shift = data_shift << 1; + end + end + end +end + +initial begin + forever begin + @ (posedge cnv) begin + data_shift = data_gen; + end + end +end + +// --------------------------------------------------------------------------- +// Generating expected data +// --------------------------------------------------------------------------- + +initial begin + forever begin + @(posedge dco_in); + if (transfer_status) begin + if (`ADC_RES == 16) begin + if (`TWOLANES == 0) begin + if (transfer_cnt[0]) begin + dma_data_store_arr[(transfer_cnt - 1) >> 1][15:0] = data_gen; + end else begin + dma_data_store_arr[(transfer_cnt - 1) >> 1][31:16] = data_gen; + end + end else begin + if (transfer_cnt[0]) begin + dma_data_store_arr[(transfer_cnt - 1) >> 1][15:0] = data_gen; + end else begin + dma_data_store_arr[(transfer_cnt - 1) >> 1][31:16] = data_gen; + end + end + end else if (`ADC_RES == 18) begin + if (`TWOLANES == 0) begin + dma_data_store_arr[(transfer_cnt - 1) >> 1] = data_gen; + end else begin + dma_data_store_arr[(transfer_cnt - 1) >> 1] = data_gen; + end + end + end + @(negedge dco_in); + end +end + +//--------------------------------------------------------------------------- +// Sanity tests +//--------------------------------------------------------------------------- + +task sanity_tests(); + //ltc2387_common_api.sanity_test(); + cn0577_dmac_api.sanity_test(); + cn0577_pwm_gen_api.sanity_test(); + `INFO(("Sanity Tests Done"), ADI_VERBOSITY_LOW); +endtask + +//--------------------------------------------------------------------------- +// Data Acquisition Test +//--------------------------------------------------------------------------- + +reg [31:0] rdata_reg; +bit [31:0] captured_word_arr [(NUM_OF_TRANSFERS) -1 :0]; +bit [31:0] config_wr_SIMPLE = 'h0; // write request sent result +bit [31:0] config_SIMPLE = 'h0; // channel static data setup + +task data_acquisition_test(); + + // Enable all ADC channels + for (int i = 0; i < 4; i=i+1) begin + ltc2387_adc_api.enable_channel( + .channel(i)); + end + + // Configure AXI PWM GEN + cn0577_pwm_gen_api.reset(); // PWM_GEN reset in regmap (ACTIVE HIGH) + + cn0577_pwm_gen_api.pulse_period_config( + .channel(8'h00), + .period(32'h1A)); + + cn0577_pwm_gen_api.pulse_width_config( + .channel(8'h00), + .width(32'h01)); + + cn0577_pwm_gen_api.pulse_period_config( + .channel(8'h01), + .period(32'h1A)); + + cn0577_pwm_gen_api.pulse_width_config( + .channel(8'h01), + .width(num_of_dco)); + + cn0577_pwm_gen_api.pulse_offset_config( + .channel(8'h01), + .offset(32'h03)); + + cn0577_pwm_gen_api.load_config(); // load AXI_PWM_GEN configuration + cn0577_pwm_gen_api.start(); + `INFO(("AXI_PWM_GEN started"), ADI_VERBOSITY_LOW); + + // Configure DMA + cn0577_dmac_api.set_irq_mask( + .transfer_completed(1'b0), + .transfer_queued(1'b1)); + cn0577_dmac_api.enable_dma(); + cn0577_dmac_api.set_flags( + .cyclic(1'b0), + .tlast(1'b1), + .partial_reporting_en(1'b1)); + cn0577_dmac_api.set_lengths( + .xfer_length_x((NUM_OF_TRANSFERS*4)-1), + .xfer_length_y(32'h0)); + cn0577_dmac_api.set_dest_addr(`DDR_BA); + + // Configure AXI_LTC2387 + ltc2387_adc_api.reset( + .ce_n(0), + .mmcm_rstn(0), + .rstn(0)); + + #5000ns; + + ltc2387_adc_api.reset( + .ce_n(0), + .mmcm_rstn(1), + .rstn(1)); + + @(posedge cnv) + #200ns; + + transfer_status = 1; + + cn0577_dmac_api.transfer_start(); + + wait(transfer_cnt == 2 * NUM_OF_TRANSFERS ); + + #100ns; + @(negedge cnv); + @(posedge ref_clk); + transfer_status = 0; + + //@(posedge system_tb.test_harness.axi_ltc2387_dma.irq); + + // Clear interrupt + cn0577_dmac_api.clear_irq_pending( + .transfer_completed(1'b1), + .transfer_queued(1'b0)); + + // Stop pwm gen + cn0577_pwm_gen_api.reset(); + `INFO(("AXI_PWM_GEN stopped"), ADI_VERBOSITY_LOW); + + // Configure axi_ltc2387 + ltc2387_adc_api.reset( + .ce_n(0), + .mmcm_rstn(1), + .rstn(1)); // bring out of reset + + ltc2387_adc_api.set_adc_config_wr( + .cfg(32'h00002181)); // set static data setup in device's reg 0x21 + + ltc2387_adc_api.get_adc_config_wr( + .cfg(config_SIMPLE)); // read last config result + `INFO(("Config_SIMPLE is set up, ADC_CONFIG_WR contains 0x%h",config_SIMPLE), ADI_VERBOSITY_LOW); + + ltc2387_adc_api.set_adc_config_control( + .cfg(32'h00000001)); // send WR request + + ltc2387_adc_api.set_adc_config_control( + .cfg(config_wr_SIMPLE)); // read last config result + `INFO(("Write request sent, ADC_CONFIG_CTRL contains 0x%h",config_wr_SIMPLE), ADI_VERBOSITY_LOW); + + ltc2387_adc_api.set_adc_config_control( + .cfg(32'h00000000)); // set default control value (no rd/wr request) + + ltc2387_adc_api.set_adc_config_control( + .cfg(config_wr_SIMPLE)); // read last config result + `INFO(("ADC_CONFIG_CTRL contains 0x%h",config_wr_SIMPLE), ADI_VERBOSITY_LOW); + + ltc2387_adc_api.set_adc_config_wr( + .cfg(32'h00000000)); // set exit from register mode sequence + + ltc2387_adc_api.set_adc_config_control( + .cfg(32'h00000001)); // send WR request + + ltc2387_adc_api.set_adc_config_control( + .cfg(32'h00000000)); // set default control value (no rd/wr request) + + //set HDL config mode + ltc2387_adc_api.set_common_control_3( + .crc_en(0), + .custom_control('h100)); // set default + + #2000ns; + for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin + #1ns; + captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); + end + + `INFO(("captured_word_arr: %x; dma_data_store_arr %x", captured_word_arr, dma_data_store_arr), ADI_VERBOSITY_LOW); + + if (captured_word_arr != dma_data_store_arr) begin + `ERROR(("Data Acquisition Test FAILED")); + end else begin + `INFO(("Data Acquisition Test PASSED"), ADI_VERBOSITY_LOW); + end + +endtask + +endprogram diff --git a/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg b/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg new file mode 100644 index 000000000..8590ac876 --- /dev/null +++ b/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg @@ -0,0 +1,160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ref_clk + ref_clk + + + clk_gate + clk_gate + + + dco_in + dco_in + + + dco_p + dco_p + + + da_p + da_p + + + db_p + db_p + + + cnv + cnv + + + data_gen[15:0] + data_gen[15:0] + + + data_shift[15:0] + data_shift[15:0] + + + transfer_status + transfer_status + + + da_p_int_s + da_p_int_s + #FFFF00 + true + + + da_n_int_s + da_n_int_s + + + adc_data_da_p[9:0] + adc_data_da_p[9:0] + + + adc_data_da_n[9:0] + adc_data_da_n[9:0] + + + adc_data_db_p[9:0] + adc_data_db_p[9:0] + + + adc_data_db_n[9:0] + adc_data_db_n[9:0] + + + adc_data_int[17:0] + adc_data_int[17:0] + + + adc_valid + adc_valid + + + adc_data[17:0] + adc_data[17:0] + + + if + label + + + dco + dco + + + dco_p + dco_p + + + da_p + da_p + + + da_p_int_s + da_p_int_s + + From 7c2548576b78ab8b102509786824f8dcad1e358f Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Thu, 23 Oct 2025 17:17:15 +0300 Subject: [PATCH 02/10] cn0577_adaq2387x: Update Makefile Signed-off-by: Stanca Pop --- testbenches/project/cn0577_adaq2387x/Makefile | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/testbenches/project/cn0577_adaq2387x/Makefile b/testbenches/project/cn0577_adaq2387x/Makefile index f540dda5f..d1dbd5f2a 100644 --- a/testbenches/project/cn0577_adaq2387x/Makefile +++ b/testbenches/project/cn0577_adaq2387x/Makefile @@ -16,27 +16,26 @@ LIB_DEPS += axi_pwm_gen LIB_DEPS += axi_dmac LIB_DEPS += axi_ltc2387 -# default test programs -# Format is: +# list of test programs TP := $(notdir $(basename $(wildcard tests/*.sv))) # config files should have the following format -# cfg__.tcl +# cfg__.tcl CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl)) # List of tests and configuration combinations that has to be run -# Format is: : -TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(addprefix $(cfg):, $(TP))) +# Format is: : +TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP)) include $(ADI_TB_DIR)/scripts/project-sim.mk # usage : # # run specific test on a specific configuration in gui mode -# make CFG=cfg1 TST=test_program MODE=gui +# make CCFG= TST= MODE=gui # # run all test from a configuration -# make cfg1 +# make #################################################################################### #################################################################################### From d4f683d915de5334384805ef4a3bcdfc7756545e Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Mon, 27 Oct 2025 14:30:43 +0200 Subject: [PATCH 03/10] cn0577_adaq2387x: PR changes Signed-off-by: Stanca Pop --- testbenches/project/cn0577_adaq2387x/Makefile | 2 +- .../project/cn0577_adaq2387x/system_bd.tcl | 7 +- .../cn0577_adaq2387x/system_project.tcl | 5 - .../project/cn0577_adaq2387x/system_tb.sv | 33 +---- .../cn0577_adaq2387x/tests/test_program.sv | 119 +++++++++--------- .../waves/system_tb_behav.wcfg | 45 +++---- 6 files changed, 83 insertions(+), 128 deletions(-) diff --git a/testbenches/project/cn0577_adaq2387x/Makefile b/testbenches/project/cn0577_adaq2387x/Makefile index d1dbd5f2a..e06a5b4a0 100644 --- a/testbenches/project/cn0577_adaq2387x/Makefile +++ b/testbenches/project/cn0577_adaq2387x/Makefile @@ -32,7 +32,7 @@ include $(ADI_TB_DIR)/scripts/project-sim.mk # usage : # # run specific test on a specific configuration in gui mode -# make CCFG= TST= MODE=gui +# make CFG= TST= MODE=gui # # run all test from a configuration # make diff --git a/testbenches/project/cn0577_adaq2387x/system_bd.tcl b/testbenches/project/cn0577_adaq2387x/system_bd.tcl index 1233d0160..2786b652e 100644 --- a/testbenches/project/cn0577_adaq2387x/system_bd.tcl +++ b/testbenches/project/cn0577_adaq2387x/system_bd.tcl @@ -41,10 +41,6 @@ set ADC_RES $ad_project_params(ADC_RES) set CN0577_ADAQ2387X_N $ad_project_params(CN0577_ADAQ2387X_N) set USE_MMCM $ad_project_params(USE_MMCM) -adi_project_files [list \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ -] - # # Block design under test # @@ -55,6 +51,9 @@ if {$CN0577_ADAQ2387X_N == 1} { source $ad_hdl_dir/projects/adaq2387x/common/adaq2387x_bd.tcl } +ad_disconnect sys_200m_clk axi_ltc2387/delay_clk +ad_connect sys_dma_clk axi_ltc2387/delay_clk + set BA_AXI_LTC2387 0x44A00000 set_property offset $BA_AXI_LTC2387 [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387}] adi_sim_add_define "AXI_LTC2387_BA=[format "%d" ${BA_AXI_LTC2387}]" diff --git a/testbenches/project/cn0577_adaq2387x/system_project.tcl b/testbenches/project/cn0577_adaq2387x/system_project.tcl index dcb396df4..885a160d3 100644 --- a/testbenches/project/cn0577_adaq2387x/system_project.tcl +++ b/testbenches/project/cn0577_adaq2387x/system_project.tcl @@ -16,11 +16,6 @@ set project_name [file rootname $cfg_file] # Set project params global ad_project_params -set TWOLANES $ad_project_params(TWOLANES) -set ADC_RES $ad_project_params(ADC_RES) -set CN0577_ADAQ2387X_N $ad_project_params(CN0577_ADAQ2387X_N) -set USE_MMCM $ad_project_params(USE_MMCM) - # Set to use SmartConnect or AXI Interconnect set use_smartconnect 1 diff --git a/testbenches/project/cn0577_adaq2387x/system_tb.sv b/testbenches/project/cn0577_adaq2387x/system_tb.sv index e9a1ee4ca..c3d60717d 100644 --- a/testbenches/project/cn0577_adaq2387x/system_tb.sv +++ b/testbenches/project/cn0577_adaq2387x/system_tb.sv @@ -39,9 +39,6 @@ module system_tb(); - // dco delay compared to the reference clk - localparam DCO_DELAY = 12; - // reg signals reg ref_clk = 1'b0; @@ -55,44 +52,18 @@ module system_tb(); reg db_p = 1'b0; reg db_n = 1'b0; - // dma interface - - wire adc_valid; - wire [`ADC_RES-1:0] adc_data; - reg adc_dovf = 1'b0; - wire cnv; - reg dco = 1'b0; - - integer cnv_count = 0; // test bench variables always #25 ref_clk = ~ref_clk; - // --------------------------------------------------------------------------- - // Creating a "gate" through which the data clock can run (and only then) - // --------------------------------------------------------------------------- - always @ (*) begin - if (clk_gate == 1'b1) begin - dco_init = ref_clk; - end else begin - dco_init = 1'b0; - end - end - - // Data clocks generation - // --------------------------------------------------------------------------- - - always @ (dco_init) begin - dco_p <= #DCO_DELAY dco_init; - dco_n <= #DCO_DELAY ~dco_init; - end - `TEST_PROGRAM test( .ref_clk (ref_clk), .clk_gate (clk_gate), .dco_in (dco_init), + .dco_p (dco_p), + .dco_n (dco_n), .da_p (da_p), .da_n (da_n), .db_p (db_p), diff --git a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv index 0e2b1a160..f0c23e1e6 100644 --- a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv +++ b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv @@ -49,10 +49,6 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; localparam NUM_OF_TRANSFERS = 16; -//--------------------------------------------------------------------------- -// SPI Engine configuration parameters -//--------------------------------------------------------------------------- - program test_program ( input ref_clk, input clk_gate, @@ -68,26 +64,13 @@ program test_program ( timeunit 1ns; timeprecision 1ps; -typedef enum {DATA_MODE_RANDOM, DATA_MODE_RAMP, DATA_MODE_PATTERN} offload_test_t; - test_harness_env #(`AXI_VIP_PARAMS(test_harness, mng_axi_vip), `AXI_VIP_PARAMS(test_harness, ddr_axi_vip)) base_env; -// set to active debug messages -localparam bit DEBUG = 1; - -// dco delay compared to the reference clk -localparam DCO_DELAY = 12; - -dmac_api cn0577_dmac_api; -pwm_gen_api cn0577_pwm_gen_api; +dmac_api dmac_api_inst; +pwm_gen_api pwm_gen_api_inst; adc_api ltc2387_adc_api; common_api ltc2387_common_api; -// dma interface -wire adc_valid; -wire [`ADC_RES-1:0] adc_data; -reg adc_dovf = 1'b0; - // -------------------------- // Main procedure // -------------------------- @@ -102,12 +85,13 @@ initial begin `TH.`SYS_RST.inst.IF, `TH.`MNG_AXI.inst.IF, `TH.`DDR_AXI.inst.IF); - cn0577_dmac_api = new( + + dmac_api_inst = new( "CN0577 DMAC API", base_env.mng.sequencer, `AXI_LTC2387_DMA_BA); - cn0577_pwm_gen_api = new( + pwm_gen_api_inst = new( "CN0577 AXI PWM GEN API", base_env.mng.sequencer, `AXI_PWM_GEN_BA); @@ -122,13 +106,13 @@ initial begin base_env.mng.sequencer, `AXI_LTC2387_BA); + setLoggerVerbosity(ADI_VERBOSITY_NONE); + base_env.start(); base_env.sys_reset(); sanity_tests(); - #100ns; - data_acquisition_test(); base_env.stop(); @@ -168,12 +152,34 @@ localparam int N = (`TWOLANES == 0 && `ADC_RES == 16) ? 16 : -1; // Error case parameter int num_of_dco = N / 2; +// dco delay compared to the reference clk +localparam DCO_DELAY = 12; + +reg dco_init = 1'b0; + + // --------------------------------------------------------------------------- + // Creating a "gate" through which the data clock can run (and only then) + // --------------------------------------------------------------------------- + + initial begin + forever begin + if (clk_gate == 1'b1) begin + dco_init = ref_clk; + end else begin + dco_init = 1'b0; + end + end +end + + // --------------------------------------------------------------------------- + // Data clocks generation + // --------------------------------------------------------------------------- + initial begin forever begin @(posedge dco_in, negedge dco_in) begin - #1 - dco_p <= dco_in; - dco_n <= ~dco_in; + dco_p <= #DCO_DELAY dco_init; + dco_n <= #DCO_DELAY ~dco_init; end end end @@ -265,8 +271,8 @@ end task sanity_tests(); //ltc2387_common_api.sanity_test(); - cn0577_dmac_api.sanity_test(); - cn0577_pwm_gen_api.sanity_test(); + dmac_api_inst.sanity_test(); + pwm_gen_api_inst.sanity_test(); `INFO(("Sanity Tests Done"), ADI_VERBOSITY_LOW); endtask @@ -288,45 +294,45 @@ task data_acquisition_test(); end // Configure AXI PWM GEN - cn0577_pwm_gen_api.reset(); // PWM_GEN reset in regmap (ACTIVE HIGH) + pwm_gen_api_inst.reset(); // PWM_GEN reset in regmap (ACTIVE HIGH) - cn0577_pwm_gen_api.pulse_period_config( - .channel(8'h00), - .period(32'h1A)); + pwm_gen_api_inst.pulse_period_config( + .channel(8'd0), + .period(32'd26)); - cn0577_pwm_gen_api.pulse_width_config( - .channel(8'h00), - .width(32'h01)); + pwm_gen_api_inst.pulse_width_config( + .channel(8'd0), + .width(32'd1)); - cn0577_pwm_gen_api.pulse_period_config( - .channel(8'h01), - .period(32'h1A)); + pwm_gen_api_inst.pulse_period_config( + .channel(8'd1), + .period(32'd26)); - cn0577_pwm_gen_api.pulse_width_config( - .channel(8'h01), + pwm_gen_api_inst.pulse_width_config( + .channel(8'd1), .width(num_of_dco)); - cn0577_pwm_gen_api.pulse_offset_config( - .channel(8'h01), - .offset(32'h03)); + pwm_gen_api_inst.pulse_offset_config( + .channel(8'd1), + .offset(32'd3)); - cn0577_pwm_gen_api.load_config(); // load AXI_PWM_GEN configuration - cn0577_pwm_gen_api.start(); + pwm_gen_api_inst.load_config(); // load AXI_PWM_GEN configuration + pwm_gen_api_inst.start(); `INFO(("AXI_PWM_GEN started"), ADI_VERBOSITY_LOW); // Configure DMA - cn0577_dmac_api.set_irq_mask( + dmac_api_inst.set_irq_mask( .transfer_completed(1'b0), .transfer_queued(1'b1)); - cn0577_dmac_api.enable_dma(); - cn0577_dmac_api.set_flags( + dmac_api_inst.enable_dma(); + dmac_api_inst.set_flags( .cyclic(1'b0), .tlast(1'b1), .partial_reporting_en(1'b1)); - cn0577_dmac_api.set_lengths( + dmac_api_inst.set_lengths( .xfer_length_x((NUM_OF_TRANSFERS*4)-1), .xfer_length_y(32'h0)); - cn0577_dmac_api.set_dest_addr(`DDR_BA); + dmac_api_inst.set_dest_addr(`DDR_BA); // Configure AXI_LTC2387 ltc2387_adc_api.reset( @@ -346,7 +352,7 @@ task data_acquisition_test(); transfer_status = 1; - cn0577_dmac_api.transfer_start(); + dmac_api_inst.transfer_start(); wait(transfer_cnt == 2 * NUM_OF_TRANSFERS ); @@ -358,19 +364,19 @@ task data_acquisition_test(); //@(posedge system_tb.test_harness.axi_ltc2387_dma.irq); // Clear interrupt - cn0577_dmac_api.clear_irq_pending( + dmac_api_inst.clear_irq_pending( .transfer_completed(1'b1), .transfer_queued(1'b0)); // Stop pwm gen - cn0577_pwm_gen_api.reset(); + pwm_gen_api_inst.reset(); `INFO(("AXI_PWM_GEN stopped"), ADI_VERBOSITY_LOW); // Configure axi_ltc2387 ltc2387_adc_api.reset( - .ce_n(0), - .mmcm_rstn(1), - .rstn(1)); // bring out of reset + .ce_n(1'b0), + .mmcm_rstn(1'b1), + .rstn(1'b1)); // bring out of reset ltc2387_adc_api.set_adc_config_wr( .cfg(32'h00002181)); // set static data setup in device's reg 0x21 @@ -409,7 +415,6 @@ task data_acquisition_test(); #2000ns; for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin - #1ns; captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); end diff --git a/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg b/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg index 8590ac876..b1a0f33d3 100644 --- a/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg +++ b/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg @@ -5,7 +5,9 @@ - + + + @@ -17,32 +19,23 @@ - - + + + - - - - - - - - - - @@ -50,15 +43,15 @@ - - - + + + - + - + ref_clk ref_clk @@ -88,12 +81,12 @@ cnv - data_gen[15:0] - data_gen[15:0] + data_gen[17:0] + data_gen[17:0] - data_shift[15:0] - data_shift[15:0] + data_shift[17:0] + data_shift[17:0] transfer_status @@ -129,14 +122,6 @@ adc_data_int[17:0] adc_data_int[17:0] - - adc_valid - adc_valid - - - adc_data[17:0] - adc_data[17:0] - if label From 0db5236786706ac2aedd583f8b5e4809acc4fbf0 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Mon, 3 Nov 2025 15:57:02 +0200 Subject: [PATCH 04/10] cn0577_adaq2387x: Generate ref_clk using VIP, update dco generation Signed-off-by: Stanca Pop --- .../project/cn0577_adaq2387x/system_bd.tcl | 23 +++++++++++++++++++ .../project/cn0577_adaq2387x/system_tb.sv | 14 +++-------- .../cn0577_adaq2387x/tests/test_program.sv | 20 ++++++++++------ 3 files changed, 39 insertions(+), 18 deletions(-) diff --git a/testbenches/project/cn0577_adaq2387x/system_bd.tcl b/testbenches/project/cn0577_adaq2387x/system_bd.tcl index 2786b652e..2e4582dc3 100644 --- a/testbenches/project/cn0577_adaq2387x/system_bd.tcl +++ b/testbenches/project/cn0577_adaq2387x/system_bd.tcl @@ -54,6 +54,29 @@ if {$CN0577_ADAQ2387X_N == 1} { ad_disconnect sys_200m_clk axi_ltc2387/delay_clk ad_connect sys_dma_clk axi_ltc2387/delay_clk +delete_bd_objs [get_bd_nets ref_clk_1] + +if {$CN0577_ADAQ2387X_N == 1} { + # 120MHz ref_clk for cn0577 + set ref_freq 120000000 +} else { + # 100Mhz ref_clk for adaq2387x + set ref_freq 100000000 +} + +ad_ip_instance clk_vip ref_clk_vip [ list \ + INTERFACE_MODE {MASTER} \ + FREQ_HZ $ref_freq \ +] + +adi_sim_add_define "REF_CLK=ref_clk_vip" + +create_bd_port -dir O ref_clk_out +ad_connect ref_clk_out ref_clk_vip/clk_out +ad_connect axi_ltc2387/ref_clk ref_clk_vip/clk_out +ad_connect axi_ltc2387_dma/fifo_wr_clk ref_clk_vip/clk_out +ad_connect axi_pwm_gen/ext_clk ref_clk_vip/clk_out + set BA_AXI_LTC2387 0x44A00000 set_property offset $BA_AXI_LTC2387 [get_bd_addr_segs {mng_axi_vip/Master_AXI/SEG_data_axi_ltc2387}] adi_sim_add_define "AXI_LTC2387_BA=[format "%d" ${BA_AXI_LTC2387}]" diff --git a/testbenches/project/cn0577_adaq2387x/system_tb.sv b/testbenches/project/cn0577_adaq2387x/system_tb.sv index c3d60717d..c2e0cc37b 100644 --- a/testbenches/project/cn0577_adaq2387x/system_tb.sv +++ b/testbenches/project/cn0577_adaq2387x/system_tb.sv @@ -41,12 +41,9 @@ module system_tb(); // reg signals - reg ref_clk = 1'b0; reg dco_init = 1'b0; - reg cnv_out = 1'b0; + reg ref_clk_out = 1'b0; reg clk_gate = 1'b0; - reg dco_p; - reg dco_n; reg da_p = 1'b0; reg da_n = 1'b0; reg db_p = 1'b0; @@ -56,10 +53,8 @@ module system_tb(); // test bench variables - always #25 ref_clk = ~ref_clk; - `TEST_PROGRAM test( - .ref_clk (ref_clk), + .ref_clk_out (ref_clk_out), .clk_gate (clk_gate), .dco_in (dco_init), .dco_p (dco_p), @@ -71,10 +66,7 @@ module system_tb(); .cnv (cnv)); test_harness `TH ( - .ref_clk (ref_clk), - .sampling_clk (sampling_clk), - .dco_p (dco_p), - .dco_n (dco_n), + .ref_clk_out (ref_clk_out), .cnv (cnv), .da_n (da_n), .da_p (da_p), diff --git a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv index f0c23e1e6..393591ae9 100644 --- a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv +++ b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv @@ -50,7 +50,7 @@ import `PKGIFY(test_harness, ddr_axi_vip)::*; localparam NUM_OF_TRANSFERS = 16; program test_program ( - input ref_clk, + input ref_clk_out, input clk_gate, input dco_in, output da_n, @@ -109,6 +109,9 @@ initial begin setLoggerVerbosity(ADI_VERBOSITY_NONE); base_env.start(); + + `TH.`REF_CLK.inst.IF.start_clock(); + base_env.sys_reset(); sanity_tests(); @@ -117,6 +120,8 @@ initial begin base_env.stop(); + `TH.`REF_CLK.inst.IF.stop_clock(); + `INFO(("Test Done"), ADI_VERBOSITY_NONE); $finish(); @@ -163,11 +168,12 @@ reg dco_init = 1'b0; initial begin forever begin - if (clk_gate == 1'b1) begin - dco_init = ref_clk; - end else begin - dco_init = 1'b0; - end + @(posedge clk_gate, negedge clk_gate) + if (clk_gate == 1'b1) begin + dco_init = ref_clk_out; + end else begin + dco_init = 1'b0; + end end end @@ -358,7 +364,7 @@ task data_acquisition_test(); #100ns; @(negedge cnv); - @(posedge ref_clk); + @(posedge ref_clk_out); transfer_status = 0; //@(posedge system_tb.test_harness.axi_ltc2387_dma.irq); From 621d1813f607224c049f59bb79d0a371ddd4afad Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Thu, 6 Nov 2025 11:56:33 +0200 Subject: [PATCH 05/10] cn0577: Fix cn0577 test program Signed-off-by: Stanca Pop --- .../project/cn0577_adaq2387x/system_bd.tcl | 3 + .../project/cn0577_adaq2387x/system_tb.sv | 23 +++-- .../cn0577_adaq2387x/tests/test_program.sv | 86 +++++++++++-------- .../waves/system_tb_behav.wcfg | 22 +++-- 4 files changed, 77 insertions(+), 57 deletions(-) diff --git a/testbenches/project/cn0577_adaq2387x/system_bd.tcl b/testbenches/project/cn0577_adaq2387x/system_bd.tcl index 2e4582dc3..1592512a5 100644 --- a/testbenches/project/cn0577_adaq2387x/system_bd.tcl +++ b/testbenches/project/cn0577_adaq2387x/system_bd.tcl @@ -51,11 +51,14 @@ if {$CN0577_ADAQ2387X_N == 1} { source $ad_hdl_dir/projects/adaq2387x/common/adaq2387x_bd.tcl } +ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 0 + ad_disconnect sys_200m_clk axi_ltc2387/delay_clk ad_connect sys_dma_clk axi_ltc2387/delay_clk delete_bd_objs [get_bd_nets ref_clk_1] + if {$CN0577_ADAQ2387X_N == 1} { # 120MHz ref_clk for cn0577 set ref_freq 120000000 diff --git a/testbenches/project/cn0577_adaq2387x/system_tb.sv b/testbenches/project/cn0577_adaq2387x/system_tb.sv index c2e0cc37b..3c809dbd5 100644 --- a/testbenches/project/cn0577_adaq2387x/system_tb.sv +++ b/testbenches/project/cn0577_adaq2387x/system_tb.sv @@ -39,24 +39,21 @@ module system_tb(); - // reg signals - - reg dco_init = 1'b0; - reg ref_clk_out = 1'b0; - reg clk_gate = 1'b0; - reg da_p = 1'b0; - reg da_n = 1'b0; - reg db_p = 1'b0; - reg db_n = 1'b0; - - wire cnv; + wire ref_clk_out; + wire clk_gate; + wire da_p; + wire da_n; + wire db_p; + wire db_n; + wire dco_p; + wire dco_n; + wire cnv; // test bench variables `TEST_PROGRAM test( .ref_clk_out (ref_clk_out), .clk_gate (clk_gate), - .dco_in (dco_init), .dco_p (dco_p), .dco_n (dco_n), .da_p (da_p), @@ -72,6 +69,8 @@ module system_tb(); .da_p (da_p), .db_n (db_n), .db_p (db_p), + .dco_p (dco_p), + .dco_n(dco_n), .clk_gate (clk_gate)); endmodule diff --git a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv index 393591ae9..66d9c85ee 100644 --- a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv +++ b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv @@ -52,7 +52,6 @@ localparam NUM_OF_TRANSFERS = 16; program test_program ( input ref_clk_out, input clk_gate, - input dco_in, output da_n, output da_p, output db_n, @@ -158,37 +157,42 @@ localparam int N = (`TWOLANES == 0 && `ADC_RES == 16) ? 16 : parameter int num_of_dco = N / 2; // dco delay compared to the reference clk -localparam DCO_DELAY = 12; +//localparam DCO_DELAY = 12; +localparam DCO_DELAY = 4; -reg dco_init = 1'b0; +// --------------------------------------------------------------------------- +// Creating a "gate" through which the data clock can run (and only then) +// --------------------------------------------------------------------------- - // --------------------------------------------------------------------------- - // Creating a "gate" through which the data clock can run (and only then) - // --------------------------------------------------------------------------- +reg dco_init; - initial begin +initial begin + dco_init = 1'b0; forever begin - @(posedge clk_gate, negedge clk_gate) - if (clk_gate == 1'b1) begin - dco_init = ref_clk_out; - end else begin - dco_init = 1'b0; - end + @(posedge ref_clk_out, negedge ref_clk_out) begin + dco_init = clk_gate ? ref_clk_out : 1'b0; + end end end - // --------------------------------------------------------------------------- - // Data clocks generation - // --------------------------------------------------------------------------- +// --------------------------------------------------------------------------- +// Data clocks generation +// --------------------------------------------------------------------------- initial begin + dco_p = 1'b0; + dco_n = 1'b1; forever begin - @(posedge dco_in, negedge dco_in) begin + @(posedge dco_init) begin + dco_p <= #DCO_DELAY dco_init; + dco_n <= #DCO_DELAY ~dco_init; + end + @(negedge dco_init) begin dco_p <= #DCO_DELAY dco_init; dco_n <= #DCO_DELAY ~dco_init; end end - end +end //--------------------------------------------------------------------------- // Data store @@ -196,11 +200,10 @@ initial begin reg [`ADC_RES-1:0] data_gen = 'h3a5a5; reg [`ADC_RES-1:0] data_shift = 'h0; - -reg r_da_p = 1'b0; -reg r_da_n = 1'b0; -reg r_db_p = 1'b0; -reg r_db_n = 1'b0; +reg r_da_p; +reg r_da_n; +reg r_db_p; +reg r_db_n; assign da_p = r_da_p; assign da_n = r_da_n; @@ -213,18 +216,29 @@ assign db_n = r_db_n; initial begin forever begin - @ (posedge dco_in, negedge dco_in) begin - if (`TWOLANES == 1) begin - r_da_p = data_shift[`ADC_RES - 1]; - r_da_n = ~data_shift[`ADC_RES - 1]; - r_db_p = data_shift[`ADC_RES - 2]; - r_db_n = ~data_shift[`ADC_RES - 2]; - data_shift = data_shift << 2; - end else begin - r_da_p = data_shift[`ADC_RES - 1]; - r_da_n = ~data_shift[`ADC_RES - 1]; - data_shift = data_shift << 1; + @(posedge dco_init, negedge dco_init) begin + if (`TWOLANES == 1) begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + r_db_p = data_shift[`ADC_RES - 2]; + r_db_n = ~data_shift[`ADC_RES - 2]; + data_shift = data_shift << 2; + end else begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + data_shift = data_shift << 1; + end end + end +end + +initial begin + forever begin + @(negedge clk_gate) begin + r_da_p = 1'b0; + r_da_n = 1'b0; + r_db_p = 1'b0; + r_db_n = 1'b0; end end end @@ -243,7 +257,7 @@ end initial begin forever begin - @(posedge dco_in); + @(posedge dco_init); if (transfer_status) begin if (`ADC_RES == 16) begin if (`TWOLANES == 0) begin @@ -267,7 +281,7 @@ initial begin end end end - @(negedge dco_in); + @(negedge dco_init); end end diff --git a/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg b/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg index b1a0f33d3..57d88a528 100644 --- a/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg +++ b/testbenches/project/cn0577_adaq2387x/waves/system_tb_behav.wcfg @@ -43,23 +43,27 @@ - - - + + + - + - - - ref_clk - ref_clk - + clk_gate clk_gate + + ref_clk_out + ref_clk_out + + + dco_init + dco_init + dco_in dco_in From 263be7eca759b840820d75186928621eb2ee7a98 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Mon, 24 Nov 2025 15:51:20 +0200 Subject: [PATCH 06/10] cn0577: PR changes - cleanup Signed-off-by: Stanca Pop --- .../project/cn0577_adaq2387x/system_bd.tcl | 5 +-- .../project/cn0577_adaq2387x/system_tb.sv | 42 +++++++++---------- .../cn0577_adaq2387x/tests/test_program.sv | 3 +- 3 files changed, 23 insertions(+), 27 deletions(-) diff --git a/testbenches/project/cn0577_adaq2387x/system_bd.tcl b/testbenches/project/cn0577_adaq2387x/system_bd.tcl index 1592512a5..a1a2fa97d 100644 --- a/testbenches/project/cn0577_adaq2387x/system_bd.tcl +++ b/testbenches/project/cn0577_adaq2387x/system_bd.tcl @@ -36,10 +36,7 @@ global ad_project_params # system level parameters -set TWOLANES $ad_project_params(TWOLANES) -set ADC_RES $ad_project_params(ADC_RES) set CN0577_ADAQ2387X_N $ad_project_params(CN0577_ADAQ2387X_N) -set USE_MMCM $ad_project_params(USE_MMCM) # # Block design under test @@ -53,6 +50,8 @@ if {$CN0577_ADAQ2387X_N == 1} { ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 0 +delete_bd_objs [get_bd_nets sys_200m_clk] + ad_disconnect sys_200m_clk axi_ltc2387/delay_clk ad_connect sys_dma_clk axi_ltc2387/delay_clk diff --git a/testbenches/project/cn0577_adaq2387x/system_tb.sv b/testbenches/project/cn0577_adaq2387x/system_tb.sv index 3c809dbd5..47eb1a09a 100644 --- a/testbenches/project/cn0577_adaq2387x/system_tb.sv +++ b/testbenches/project/cn0577_adaq2387x/system_tb.sv @@ -49,29 +49,27 @@ module system_tb(); wire dco_n; wire cnv; - // test bench variables + `TEST_PROGRAM test( + .ref_clk_out (ref_clk_out), + .clk_gate (clk_gate), + .dco_p (dco_p), + .dco_n (dco_n), + .da_p (da_p), + .da_n (da_n), + .db_p (db_p), + .db_n (db_n), + .cnv (cnv)); - `TEST_PROGRAM test( - .ref_clk_out (ref_clk_out), - .clk_gate (clk_gate), - .dco_p (dco_p), - .dco_n (dco_n), - .da_p (da_p), - .da_n (da_n), - .db_p (db_p), - .db_n (db_n), - .cnv (cnv)); - - test_harness `TH ( - .ref_clk_out (ref_clk_out), - .cnv (cnv), - .da_n (da_n), - .da_p (da_p), - .db_n (db_n), - .db_p (db_p), - .dco_p (dco_p), - .dco_n(dco_n), - .clk_gate (clk_gate)); + test_harness `TH ( + .ref_clk_out (ref_clk_out), + .cnv (cnv), + .da_n (da_n), + .da_p (da_p), + .db_n (db_n), + .db_p (db_p), + .dco_p (dco_p), + .dco_n(dco_n), + .clk_gate (clk_gate)); endmodule diff --git a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv index 66d9c85ee..be9de119f 100644 --- a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv +++ b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv @@ -156,8 +156,7 @@ localparam int N = (`TWOLANES == 0 && `ADC_RES == 16) ? 16 : -1; // Error case parameter int num_of_dco = N / 2; -// dco delay compared to the reference clk -//localparam DCO_DELAY = 12; +// dco delay compared to the reference clk, expressed in ns localparam DCO_DELAY = 4; // --------------------------------------------------------------------------- From b95b0ae0a4d71c078a81b6498b2dc7dbabd2ea0a Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Tue, 25 Nov 2025 11:11:58 +0200 Subject: [PATCH 07/10] cn0577_adaq2387x: Randomize data, fix indentation Signed-off-by: Stanca Pop --- .../cn0577_adaq2387x/tests/test_program.sv | 23 ++++++++++--------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv index be9de119f..39ad19e97 100644 --- a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv +++ b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv @@ -216,18 +216,18 @@ assign db_n = r_db_n; initial begin forever begin @(posedge dco_init, negedge dco_init) begin - if (`TWOLANES == 1) begin - r_da_p = data_shift[`ADC_RES - 1]; - r_da_n = ~data_shift[`ADC_RES - 1]; - r_db_p = data_shift[`ADC_RES - 2]; - r_db_n = ~data_shift[`ADC_RES - 2]; - data_shift = data_shift << 2; - end else begin - r_da_p = data_shift[`ADC_RES - 1]; - r_da_n = ~data_shift[`ADC_RES - 1]; - data_shift = data_shift << 1; - end + if (`TWOLANES == 1) begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + r_db_p = data_shift[`ADC_RES - 2]; + r_db_n = ~data_shift[`ADC_RES - 2]; + data_shift = data_shift << 2; + end else begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + data_shift = data_shift << 1; end + end end end @@ -246,6 +246,7 @@ initial begin forever begin @ (posedge cnv) begin data_shift = data_gen; + data_gen = $urandom; end end end From a71cff61c138a9af31c596320816bad586f9417b Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Tue, 25 Nov 2025 12:02:29 +0200 Subject: [PATCH 08/10] cn0577_adaq2387x: Specify delay units Signed-off-by: Stanca Pop --- .../project/cn0577_adaq2387x/tests/test_program.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv index 39ad19e97..9f5395a6e 100644 --- a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv +++ b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv @@ -183,12 +183,12 @@ initial begin dco_n = 1'b1; forever begin @(posedge dco_init) begin - dco_p <= #DCO_DELAY dco_init; - dco_n <= #DCO_DELAY ~dco_init; + dco_p <= #(DCO_DELAY * 1ns) dco_init; + dco_n <= #(DCO_DELAY * 1ns) ~dco_init; end @(negedge dco_init) begin - dco_p <= #DCO_DELAY dco_init; - dco_n <= #DCO_DELAY ~dco_init; + dco_p <= #(DCO_DELAY * 1ns) dco_init; + dco_n <= #(DCO_DELAY * 1ns) ~dco_init; end end end @@ -197,7 +197,7 @@ end // Data store //--------------------------------------------------------------------------- -reg [`ADC_RES-1:0] data_gen = 'h3a5a5; +reg [`ADC_RES-1:0] data_gen = 'h3a5c2; reg [`ADC_RES-1:0] data_shift = 'h0; reg r_da_p; reg r_da_n; From 62a74ef4052cd2025e3ecf7b64e2ac54d0886a20 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Tue, 25 Nov 2025 17:01:00 +0200 Subject: [PATCH 09/10] cn0577_adaq2387x: Fix PR changes req Signed-off-by: Stanca Pop --- .../project/cn0577_adaq2387x/system_bd.tcl | 4 +- .../cn0577_adaq2387x/tests/test_program.sv | 250 +++++++++--------- 2 files changed, 129 insertions(+), 125 deletions(-) diff --git a/testbenches/project/cn0577_adaq2387x/system_bd.tcl b/testbenches/project/cn0577_adaq2387x/system_bd.tcl index a1a2fa97d..80348b749 100644 --- a/testbenches/project/cn0577_adaq2387x/system_bd.tcl +++ b/testbenches/project/cn0577_adaq2387x/system_bd.tcl @@ -50,13 +50,11 @@ if {$CN0577_ADAQ2387X_N == 1} { ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 0 -delete_bd_objs [get_bd_nets sys_200m_clk] - ad_disconnect sys_200m_clk axi_ltc2387/delay_clk ad_connect sys_dma_clk axi_ltc2387/delay_clk delete_bd_objs [get_bd_nets ref_clk_1] - +delete_bd_objs [get_bd_nets sys_200m_clk] if {$CN0577_ADAQ2387X_N == 1} { # 120MHz ref_clk for cn0577 diff --git a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv index 9f5395a6e..4d5fd49c3 100644 --- a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv +++ b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv @@ -138,7 +138,7 @@ initial begin transfer_cnt = 0; forever begin @(posedge cnv); - if (transfer_status) begin + if (transfer_status) begin transfer_cnt = transfer_cnt + 1; end @(negedge cnv); @@ -216,17 +216,17 @@ assign db_n = r_db_n; initial begin forever begin @(posedge dco_init, negedge dco_init) begin - if (`TWOLANES == 1) begin - r_da_p = data_shift[`ADC_RES - 1]; - r_da_n = ~data_shift[`ADC_RES - 1]; - r_db_p = data_shift[`ADC_RES - 2]; - r_db_n = ~data_shift[`ADC_RES - 2]; - data_shift = data_shift << 2; - end else begin - r_da_p = data_shift[`ADC_RES - 1]; - r_da_n = ~data_shift[`ADC_RES - 1]; - data_shift = data_shift << 1; - end + if (`TWOLANES == 1) begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + r_db_p = data_shift[`ADC_RES - 2]; + r_db_n = ~data_shift[`ADC_RES - 2]; + data_shift = data_shift << 2; + end else begin + r_da_p = data_shift[`ADC_RES - 1]; + r_da_n = ~data_shift[`ADC_RES - 1]; + data_shift = data_shift << 1; + end end end end @@ -244,7 +244,7 @@ end initial begin forever begin - @ (posedge cnv) begin + @(posedge cnv) begin data_shift = data_gen; data_gen = $urandom; end @@ -290,10 +290,10 @@ end //--------------------------------------------------------------------------- task sanity_tests(); - //ltc2387_common_api.sanity_test(); - dmac_api_inst.sanity_test(); - pwm_gen_api_inst.sanity_test(); - `INFO(("Sanity Tests Done"), ADI_VERBOSITY_LOW); + //ltc2387_common_api.sanity_test(); + dmac_api_inst.sanity_test(); + pwm_gen_api_inst.sanity_test(); + `INFO(("Sanity Tests Done"), ADI_VERBOSITY_LOW); endtask //--------------------------------------------------------------------------- @@ -307,144 +307,150 @@ bit [31:0] config_SIMPLE = 'h0; // channel static data setup task data_acquisition_test(); - // Enable all ADC channels - for (int i = 0; i < 4; i=i+1) begin - ltc2387_adc_api.enable_channel( - .channel(i)); - end + // Enable all ADC channels + for (int i = 0; i < 4; i=i+1) begin + ltc2387_adc_api.enable_channel( + .channel(i)); + end - // Configure AXI PWM GEN - pwm_gen_api_inst.reset(); // PWM_GEN reset in regmap (ACTIVE HIGH) + // Configure AXI PWM GEN + pwm_gen_api_inst.reset(); // PWM_GEN reset in regmap (ACTIVE HIGH) - pwm_gen_api_inst.pulse_period_config( - .channel(8'd0), - .period(32'd26)); + pwm_gen_api_inst.pulse_period_config( + .channel(8'd0), + .period(32'd26)); - pwm_gen_api_inst.pulse_width_config( - .channel(8'd0), - .width(32'd1)); + pwm_gen_api_inst.pulse_width_config( + .channel(8'd0), + .width(32'd1)); - pwm_gen_api_inst.pulse_period_config( - .channel(8'd1), - .period(32'd26)); + pwm_gen_api_inst.pulse_period_config( + .channel(8'd1), + .period(32'd26)); - pwm_gen_api_inst.pulse_width_config( - .channel(8'd1), - .width(num_of_dco)); + pwm_gen_api_inst.pulse_width_config( + .channel(8'd1), + .width(num_of_dco)); - pwm_gen_api_inst.pulse_offset_config( - .channel(8'd1), - .offset(32'd3)); + pwm_gen_api_inst.pulse_offset_config( + .channel(8'd1), + .offset(32'd3)); - pwm_gen_api_inst.load_config(); // load AXI_PWM_GEN configuration - pwm_gen_api_inst.start(); - `INFO(("AXI_PWM_GEN started"), ADI_VERBOSITY_LOW); + pwm_gen_api_inst.load_config(); // load AXI_PWM_GEN configuration - // Configure DMA - dmac_api_inst.set_irq_mask( - .transfer_completed(1'b0), - .transfer_queued(1'b1)); - dmac_api_inst.enable_dma(); - dmac_api_inst.set_flags( - .cyclic(1'b0), - .tlast(1'b1), - .partial_reporting_en(1'b1)); - dmac_api_inst.set_lengths( - .xfer_length_x((NUM_OF_TRANSFERS*4)-1), - .xfer_length_y(32'h0)); - dmac_api_inst.set_dest_addr(`DDR_BA); + pwm_gen_api_inst.start(); + `INFO(("AXI_PWM_GEN started"), ADI_VERBOSITY_LOW); - // Configure AXI_LTC2387 - ltc2387_adc_api.reset( - .ce_n(0), - .mmcm_rstn(0), - .rstn(0)); + // Configure DMA + dmac_api_inst.set_irq_mask( + .transfer_completed(1'b0), + .transfer_queued(1'b1)); - #5000ns; + dmac_api_inst.enable_dma(); - ltc2387_adc_api.reset( - .ce_n(0), - .mmcm_rstn(1), - .rstn(1)); + dmac_api_inst.set_flags( + .cyclic(1'b0), + .tlast(1'b1), + .partial_reporting_en(1'b1)); - @(posedge cnv) - #200ns; + dmac_api_inst.set_lengths( + .xfer_length_x((NUM_OF_TRANSFERS*4)-1), + .xfer_length_y(32'h0)); - transfer_status = 1; + dmac_api_inst.set_dest_addr(`DDR_BA); - dmac_api_inst.transfer_start(); + // Configure AXI_LTC2387 + ltc2387_adc_api.reset( + .ce_n(0), + .mmcm_rstn(0), + .rstn(0)); - wait(transfer_cnt == 2 * NUM_OF_TRANSFERS ); + #5000ns; - #100ns; - @(negedge cnv); - @(posedge ref_clk_out); - transfer_status = 0; + ltc2387_adc_api.reset( + .ce_n(0), + .mmcm_rstn(1), + .rstn(1)); - //@(posedge system_tb.test_harness.axi_ltc2387_dma.irq); + @(posedge cnv) + #200ns; - // Clear interrupt - dmac_api_inst.clear_irq_pending( - .transfer_completed(1'b1), - .transfer_queued(1'b0)); + transfer_status = 1; - // Stop pwm gen - pwm_gen_api_inst.reset(); - `INFO(("AXI_PWM_GEN stopped"), ADI_VERBOSITY_LOW); + dmac_api_inst.transfer_start(); - // Configure axi_ltc2387 - ltc2387_adc_api.reset( - .ce_n(1'b0), - .mmcm_rstn(1'b1), - .rstn(1'b1)); // bring out of reset + wait(transfer_cnt == 2 * NUM_OF_TRANSFERS ); - ltc2387_adc_api.set_adc_config_wr( - .cfg(32'h00002181)); // set static data setup in device's reg 0x21 + #100ns; + @(negedge cnv); + @(posedge ref_clk_out); + transfer_status = 0; - ltc2387_adc_api.get_adc_config_wr( - .cfg(config_SIMPLE)); // read last config result - `INFO(("Config_SIMPLE is set up, ADC_CONFIG_WR contains 0x%h",config_SIMPLE), ADI_VERBOSITY_LOW); + //@(posedge system_tb.test_harness.axi_ltc2387_dma.irq); - ltc2387_adc_api.set_adc_config_control( - .cfg(32'h00000001)); // send WR request + // Clear interrupt + dmac_api_inst.clear_irq_pending( + .transfer_completed(1'b1), + .transfer_queued(1'b0)); - ltc2387_adc_api.set_adc_config_control( - .cfg(config_wr_SIMPLE)); // read last config result - `INFO(("Write request sent, ADC_CONFIG_CTRL contains 0x%h",config_wr_SIMPLE), ADI_VERBOSITY_LOW); + // Stop pwm gen + pwm_gen_api_inst.reset(); + `INFO(("AXI_PWM_GEN stopped"), ADI_VERBOSITY_LOW); - ltc2387_adc_api.set_adc_config_control( - .cfg(32'h00000000)); // set default control value (no rd/wr request) + // Configure axi_ltc2387 + ltc2387_adc_api.reset( + .ce_n(1'b0), + .mmcm_rstn(1'b1), + .rstn(1'b1)); // bring out of reset - ltc2387_adc_api.set_adc_config_control( - .cfg(config_wr_SIMPLE)); // read last config result - `INFO(("ADC_CONFIG_CTRL contains 0x%h",config_wr_SIMPLE), ADI_VERBOSITY_LOW); + ltc2387_adc_api.set_adc_config_wr( + .cfg(32'h00002181)); // set static data setup in device's reg 0x21 - ltc2387_adc_api.set_adc_config_wr( - .cfg(32'h00000000)); // set exit from register mode sequence + ltc2387_adc_api.get_adc_config_wr( + .cfg(config_SIMPLE)); // read last config result + `INFO(("Config_SIMPLE is set up, ADC_CONFIG_WR contains 0x%h",config_SIMPLE), ADI_VERBOSITY_LOW); - ltc2387_adc_api.set_adc_config_control( - .cfg(32'h00000001)); // send WR request + ltc2387_adc_api.set_adc_config_control( + .cfg(32'h00000001)); // send WR request - ltc2387_adc_api.set_adc_config_control( - .cfg(32'h00000000)); // set default control value (no rd/wr request) + ltc2387_adc_api.set_adc_config_control( + .cfg(config_wr_SIMPLE)); // read last config result + `INFO(("Write request sent, ADC_CONFIG_CTRL contains 0x%h",config_wr_SIMPLE), ADI_VERBOSITY_LOW); - //set HDL config mode - ltc2387_adc_api.set_common_control_3( - .crc_en(0), - .custom_control('h100)); // set default + ltc2387_adc_api.set_adc_config_control( + .cfg(32'h00000000)); // set default control value (no rd/wr request) - #2000ns; - for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin - captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); - end + ltc2387_adc_api.set_adc_config_control( + .cfg(config_wr_SIMPLE)); // read last config result + `INFO(("ADC_CONFIG_CTRL contains 0x%h",config_wr_SIMPLE), ADI_VERBOSITY_LOW); - `INFO(("captured_word_arr: %x; dma_data_store_arr %x", captured_word_arr, dma_data_store_arr), ADI_VERBOSITY_LOW); + ltc2387_adc_api.set_adc_config_wr( + .cfg(32'h00000000)); // set exit from register mode sequence - if (captured_word_arr != dma_data_store_arr) begin - `ERROR(("Data Acquisition Test FAILED")); - end else begin - `INFO(("Data Acquisition Test PASSED"), ADI_VERBOSITY_LOW); - end + ltc2387_adc_api.set_adc_config_control( + .cfg(32'h00000001)); // send WR request + + ltc2387_adc_api.set_adc_config_control( + .cfg(32'h00000000)); // set default control value (no rd/wr request) + + //set HDL config mode + ltc2387_adc_api.set_common_control_3( + .crc_en(0), + .custom_control('h100)); // set default + + #2000ns; + + for (int i=0; i<=((NUM_OF_TRANSFERS) -1); i=i+1) begin + captured_word_arr[i] = base_env.ddr.agent.mem_model.backdoor_memory_read_4byte(xil_axi_uint'(`DDR_BA + 4*i)); + end + + `INFO(("captured_word_arr: %x; dma_data_store_arr %x", captured_word_arr, dma_data_store_arr), ADI_VERBOSITY_LOW); + + if (captured_word_arr != dma_data_store_arr) begin + `ERROR(("Data Acquisition Test FAILED")); + end else begin + `INFO(("Data Acquisition Test PASSED"), ADI_VERBOSITY_LOW); + end endtask From 7e3b39df5518ff9f5fa2ba6c412ab94d40951dfa Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Tue, 25 Nov 2025 17:23:31 +0200 Subject: [PATCH 10/10] cn0577_adaq2387x: Add param names and values Signed-off-by: Stanca Pop --- .../cn0577_adaq2387x/tests/test_program.sv | 39 ++++++++++--------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv index 4d5fd49c3..9a3df3b01 100644 --- a/testbenches/project/cn0577_adaq2387x/tests/test_program.sv +++ b/testbenches/project/cn0577_adaq2387x/tests/test_program.sv @@ -77,33 +77,34 @@ common_api ltc2387_common_api; initial begin //creating environment - base_env = new("Base Environment", - `TH.`SYS_CLK.inst.IF, - `TH.`DMA_CLK.inst.IF, - `TH.`DDR_CLK.inst.IF, - `TH.`SYS_RST.inst.IF, - `TH.`MNG_AXI.inst.IF, - `TH.`DDR_AXI.inst.IF); + base_env = new( + .name("Base Environment"), + .sys_clk_vip_if(`TH.`SYS_CLK.inst.IF), + .dma_clk_vip_if(`TH.`DMA_CLK.inst.IF), + .ddr_clk_vip_if(`TH.`DDR_CLK.inst.IF), + .sys_rst_vip_if(`TH.`SYS_RST.inst.IF), + .mng_vip_if(`TH.`MNG_AXI.inst.IF), + .ddr_vip_if(`TH.`DDR_AXI.inst.IF)); dmac_api_inst = new( - "CN0577 DMAC API", - base_env.mng.sequencer, - `AXI_LTC2387_DMA_BA); + .name("CN0577 DMAC API"), + .bus(base_env.mng.sequencer), + .base_address(`AXI_LTC2387_DMA_BA)); pwm_gen_api_inst = new( - "CN0577 AXI PWM GEN API", - base_env.mng.sequencer, - `AXI_PWM_GEN_BA); + .name("CN0577 AXI PWM GEN API"), + .bus(base_env.mng.sequencer), + .base_address(`AXI_PWM_GEN_BA)); ltc2387_adc_api = new( - "LTC2387 ADC Common API", - base_env.mng.sequencer, - `AXI_LTC2387_BA); + .name("LTC2387 ADC Common API"), + .bus(base_env.mng.sequencer), + .base_address(`AXI_LTC2387_BA)); ltc2387_common_api = new( - "LTC2387 Common API", - base_env.mng.sequencer, - `AXI_LTC2387_BA); + .name("LTC2387 Common API)", + .bus(base_env.mng.sequencer), + .base_address(`AXI_LTC2387_BA)); setLoggerVerbosity(ADI_VERBOSITY_NONE);