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IstvanZsSzekely wants to merge 36 commits into from
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Packet filter #118

IstvanZsSzekely wants to merge 36 commits into from

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@IstvanZsSzekely IstvanZsSzekely commented Aug 23, 2024 •
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PR Description

Added a packet filter base class, that can be used in the publisher-subscriber classes
Initially designed for cases where multiple data lanes can be interleaved and data needs to be filtered for validation.

Merge after: #175

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • New test (change that adds new test program and/or testbench)
  • Breaking change (has dependencies in other repositories/testbenches)
  • Documentation (change that adds or modifies documentation)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have ran all testbenches affected by this PR
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Errors on compilation/elaboration/simulation
  • I have set the verbosity level to none for the test program

@IstvanZsSzekely IstvanZsSzekely added enhancement New feature or request new New testbench labels Aug 23, 2024
@IstvanZsSzekely IstvanZsSzekely self-assigned this Aug 23, 2024
@IstvanZsSzekely IstvanZsSzekely marked this pull request as draft September 2, 2024 13:31
@IstvanZsSzekely IstvanZsSzekely marked this pull request as ready for review September 9, 2024 08:29
@IstvanZsSzekely IstvanZsSzekely mentioned this pull request Sep 10, 2024
Merged
@IstvanZsSzekely IstvanZsSzekely force-pushed the packet_filter branch 2 times, most recently from 561b8d3 to d6b046c Compare September 10, 2024 07:06
@IstvanZsSzekely IstvanZsSzekely marked this pull request as draft November 26, 2024 11:07
@IstvanZsSzekely
infrastructure refactorization
f1e88cc 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: Fixes
e0e4835 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: Refactoring
836fbe3 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: Generalized scoreboard
c99cfd7 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: Updated DMA loopback project
a463503 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: Fixed address value in DMA loopback f…
fb7eadf 
…or DDR

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: Updated IP level testbenches
5ee6bb3 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: IP level updates
29b8873 
- Fixed SPI engine environment
- Updated environment creation and macros

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: Updated Project level testbenches
53c1327 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: Updates and fixes
d2aa755 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
ad7616: Fixes
1670e8e 
- Fixed the serial test
- Parallel data acquisition test still failing

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
dma_flock: Fixed testbench after rebase
269401b 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
adi_datatypes: Added FIFO and LIFO class implementation
41dfa6f 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
infrastructure refactorization: Minor fixes
2991e44 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
util_axis_fifo_asym: Initial testbench commit
1fe651d 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
util_axis_fifo_asym: Updated after rebase
fc60809 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
util_axis_fifo_asym: Updates and fixes
2693a75 
- Extended the ADI agent with additional functions
- Fixes issues with the AXIS VIP sequencer
- Updated the testbench

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
util_axis_fifo_asym: Updated waveform configuration
98691b5 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
util_axis_fifo: Initial testbench commit
2f11dc9 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
util_axis_fifo: Updated ADI AXI and AXIS agents
76665e5 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
util_axis_fifo: Fixed ADI AXI agent run call
30018ba 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
General updates:
8ee0dee 
- Added/Updated licensce headers
- Updated testbench depndencies
- Updated class hierarchy

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
SPI VIP update
a5337ee 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
General updates: Updated VIP clocking and reset calls
a888f41 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
general: Change while(1) calls to forever
46b53bb 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
ADI AMD agent abstractization
afcd1be 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
ADI AMD agent abstractization: Added linker macro to simplify VIP lin…
e87f281 
…king

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
ADI AMD agent abstractication: Updated testbenches for the base envir…
a6483d7 
…onment

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
library/vip/amd/axi/s_axi_sequencer: Added memory access functions
a8c9d2d 
- Updated testbenches as well

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
library/vip/amd/axi/s_axi_sequencer: Cosmetic change
bf9ae58 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
library/vip/amd: Updated ADI agent function calls to fix a null-objec…
85d89c1 
…t access

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
scoreboard: Simplified to AXIS datastream verification
13863e7 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
scoreboard: Commented test program
1961396 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely IstvanZsSzekely marked this pull request as ready for review February 20, 2025 11:06
@IstvanZsSzekely
packet_filter: Initial commit
bffecca 
- Added packet filter base class
- Updated publisher with the filter class

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
packet_filter: Add dependencies
baf31fd 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
@IstvanZsSzekely
packet_filter: Add sandbox testbench
a878252 
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
This was referenced Feb 26, 2025
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@IstvanZsSzekely IstvanZsSzekely marked this pull request as draft March 18, 2025 13:41
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IstvanZsSzekely commented Nov 5, 2025

Dropping this feature in favor of separate filtering and processing classes.
This will separate the publisher-subscriber part entirely from the filtering and processing classes, keeping the classes simple and easy to use.

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@gastmaier gastmaier Awaiting requested review from gastmaier

@LBFFilho LBFFilho Awaiting requested review from LBFFilho

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