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docs/testbenches/project_based: Updated to NUM_OF_SDIO parameter
Updated from NUM_OF_SDI to NUM_OF_SDIO parameter in the documentation of the following projects: * ad463x; * ad738x; * ad7606; * pulsar_adc. Signed-off-by: Carlos Souza <carlos.souza@analog.com>
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‎docs/testbenches/project_based/ad463x/index.rst‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ The following parameters of this project that can be configured:
3535

3636
- CLK_MODE: defines clocking mode of the device's digital interface:
3737
Options: 0 - SPI mode, 1 - Echo-clock or Master clock mode
38-
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
38+
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
3939
Options: 1 - Interleaved mode, 2 - 1 lane per channel,
4040
4 - 2 lanes per channel, 8 - 4 lanes per channel
4141
- CAPTURE_ZONE: defines the capture zone of the next sample.
@@ -54,30 +54,30 @@ The following configuration files are available:
5454
+-----------------------+-----------------------------------------------+
5555
| Configuration mode | Parameters |
5656
| +----------+------------+--------------+--------+
57-
| | CLK_MODE | NUM_OF_SDI | CAPTURE_ZONE | DDR_EN |
58-
+=======================+==========+============+==============+========+
59-
| cfg_cm0_sdi2_cz1_ddr0 | 0 | 2 | 1 | 0 |
60-
+-----------------------+----------+------------+--------------+--------+
61-
| cfg_cm0_sdi2_cz2_ddr0 | 0 | 2 | 2 | 0 |
62-
+-----------------------+----------+------------+--------------+--------+
63-
| cfg_cm0_sdi4_cz2_ddr0 | 0 | 4 | 2 | 0 |
64-
+-----------------------+----------+------------+--------------+--------+
65-
| cfg_cm0_sdi8_cz2_ddr0 | 0 | 8 | 2 | 0 |
66-
+-----------------------+----------+------------+--------------+--------+
67-
| cfg_cm1_sdi1_cz2_ddr0 | 1 | 1 | 2 | 0 |
68-
+-----------------------+----------+------------+--------------+--------+
69-
| cfg_cm1_sdi2_cz2_ddr0 | 1 | 2 | 2 | 0 |
70-
+-----------------------+----------+------------+--------------+--------+
71-
| cfg_cm1_sdi2_cz2_ddr1 | 1 | 2 | 2 | 1 |
72-
+-----------------------+----------+------------+--------------+--------+
73-
| cfg_cm1_sdi4_cz2_ddr0 | 1 | 4 | 2 | 0 |
74-
+-----------------------+----------+------------+--------------+--------+
75-
| cfg_cm1_sdi4_cz2_ddr1 | 1 | 4 | 2 | 1 |
76-
+-----------------------+----------+------------+--------------+--------+
77-
| cfg_cm1_sdi8_cz2_ddr0 | 1 | 8 | 2 | 0 |
78-
+-----------------------+----------+------------+--------------+--------+
79-
| cfg_cm1_sdi8_cz2_ddr1 | 1 | 8 | 2 | 1 |
80-
+-----------------------+----------+------------+--------------+--------+
57+
| | CLK_MODE | NUM_OF_SDIO | CAPTURE_ZONE | DDR_EN |
58+
+=======================+==========+=============+==============+========+
59+
| cfg_cm0_sdi2_cz1_ddr0 | 0 | 2 | 1 | 0 |
60+
+-----------------------+----------+-------------+--------------+--------+
61+
| cfg_cm0_sdi2_cz2_ddr0 | 0 | 2 | 2 | 0 |
62+
+-----------------------+----------+-------------+--------------+--------+
63+
| cfg_cm0_sdi4_cz2_ddr0 | 0 | 4 | 2 | 0 |
64+
+-----------------------+----------+-------------+--------------+--------+
65+
| cfg_cm0_sdi8_cz2_ddr0 | 0 | 8 | 2 | 0 |
66+
+-----------------------+----------+-------------+--------------+--------+
67+
| cfg_cm1_sdi1_cz2_ddr0 | 1 | 1 | 2 | 0 |
68+
+-----------------------+----------+-------------+--------------+--------+
69+
| cfg_cm1_sdi2_cz2_ddr0 | 1 | 2 | 2 | 0 |
70+
+-----------------------+----------+-------------+--------------+--------+
71+
| cfg_cm1_sdi2_cz2_ddr1 | 1 | 2 | 2 | 1 |
72+
+-----------------------+----------+-------------+--------------+--------+
73+
| cfg_cm1_sdi4_cz2_ddr0 | 1 | 4 | 2 | 0 |
74+
+-----------------------+----------+-------------+--------------+--------+
75+
| cfg_cm1_sdi4_cz2_ddr1 | 1 | 4 | 2 | 1 |
76+
+-----------------------+----------+-------------+--------------+--------+
77+
| cfg_cm1_sdi8_cz2_ddr0 | 1 | 8 | 2 | 0 |
78+
+-----------------------+----------+-------------+--------------+--------+
79+
| cfg_cm1_sdi8_cz2_ddr1 | 1 | 8 | 2 | 1 |
80+
+-----------------------+----------+-------------+--------------+--------+
8181

8282
Tests
8383
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

‎docs/testbenches/project_based/ad738x/index.rst‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ The following parameters of this project that can be configured:
3636
- ALERT_SPI_N: defines if a known pin will operate as a serial data output pin
3737
or alert indication pin:
3838
Options: 0 - Serial Data Output Pin, 1 - Alert Indication Ouput Pin
39-
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
39+
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
4040
Options: 1 - Interleaved mode, 2 - 1 lane per channel,
4141
4 - 2 lanes per channel
4242

@@ -45,13 +45,13 @@ Configuration files
4545

4646
The following configuration files are available:
4747

48-
+-----------------------+--------------------------+
49-
| Configuration mode | Parameters |
50-
| +----------+---------------+
51-
| | ALERT_SPI_N | NUM_OF_SDI |
52-
+=======================+=============+============+
53-
| cfg1 | 0 | 2 |
54-
+-----------------------+-------------+------------+
48+
+-----------------------+---------------------------+
49+
| Configuration mode | Parameters |
50+
| +----------+----------------+
51+
| | ALERT_SPI_N | NUM_OF_SDIO |
52+
+=======================+=============+=============+
53+
| cfg1 | 0 | 2 |
54+
+-----------------------+-------------+-------------+
5555

5656
Tests
5757
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

‎docs/testbenches/project_based/ad7606/index.rst‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ The following parameters of this project that can be configured:
3939
Options: 0 - without external clock, 1 - with external clock
4040
- INTF: defines the interface type:
4141
Options: 0 - Parallel, 1 - Serial
42-
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
42+
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
4343
Options: 1 - Interleaved mode, 2 - 1 lane per channel,
4444
4 - 2 lanes per channel, 8 - 4 lanes per channel
4545

@@ -50,15 +50,15 @@ The following configuration files are available:
5050

5151
+-----------------------+------------------------------------------+
5252
| Configuration mode | Parameters |
53-
| +------------+---------+------+------------+
54-
| | DEV_CONFIG | EXT_CLK | INTF | NUM_OF_SDI |
55-
+=======================+============+=========+======+============+
56-
| cfg1 | 0 | 0 | 0 | 1 |
57-
+-----------------------+------------+---------+------+------------+
58-
| cfg2 | 1 | 0 | 0 | 1 |
59-
+-----------------------+------------+---------+------+------------+
60-
| cfg3 | 2 | 0 | 0 | 1 |
61-
+-----------------------+------------+---------+------+------------+
53+
| +------------+---------+------+-------------+
54+
| | DEV_CONFIG | EXT_CLK | INTF | NUM_OF_SDIO |
55+
+=======================+============+=========+======+=============+
56+
| cfg1 | 0 | 0 | 0 | 1 |
57+
+-----------------------+------------+---------+------+-------------+
58+
| cfg2 | 1 | 0 | 0 | 1 |
59+
+-----------------------+------------+---------+------+-------------+
60+
| cfg3 | 2 | 0 | 0 | 1 |
61+
+-----------------------+------------+---------+------+-------------+
6262

6363
Tests
6464
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

‎docs/testbenches/project_based/pulsar_adc/index.rst‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ The following parameters of this project that can be configured:
3333

3434
- CLK_MODE: defines clocking mode of the device's digital interface:
3535
Options: 0 - SPI mode
36-
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
36+
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
3737
Options: 1 - Interleaved mode
3838
- CAPTURE_ZONE: defines the capture zone of the next sample.
3939
There are two capture zones: 1 - from negative edge of the BUSY line
@@ -50,7 +50,7 @@ The following configuration file is available:
5050
+-----------------------+-----------------------------------------------+
5151
| Configuration mode | Parameters |
5252
| +----------+------------+--------------+--------+
53-
| | CLK_MODE | NUM_OF_SDI | CAPTURE_ZONE | DDR_EN |
53+
| | CLK_MODE |NUM_OF_SDIO | CAPTURE_ZONE | DDR_EN |
5454
+=======================+==========+============+==============+========+
5555
| cfg1 | 0 | 2 | 1 | 0 |
5656
+-----------------------+----------+------------+--------------+--------+

‎docs/testbenches/project_based/template/_index.rst‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ The following parameters of this project that can be configured:
5252

5353
- CLK_MODE: defines clocking mode of the device's digital interface:
5454
Options: 0 - SPI mode, 1 - Echo-clock or Master clock mode
55-
- NUM_OF_SDI: defines the number of MOSI lines of the SPI interface:
55+
- NUM_OF_SDIO: defines the number of MOSI lines of the SPI interface:
5656
Options: 1 - Interleaved mode, 2 - 1 lane per channel,
5757
4 - 2 lanes per channel, 8 - 4 lanes per channel
5858
- CAPTURE_ZONE: defines the capture zone of the next sample.
@@ -75,7 +75,7 @@ The following are available configurations for the testbench:
7575
+-----------------------+-----------------------------------------------+
7676
| Configuration mode | Parameters |
7777
| +----------+------------+--------------+--------+
78-
| | CLK_MODE | NUM_OF_SDI | CAPTURE_ZONE | DDR_EN |
78+
| | CLK_MODE |NUM_OF_SDIO | CAPTURE_ZONE | DDR_EN |
7979
+=======================+==========+============+==============+========+
8080
| cfg_cm0_sdi2_cz1_ddr0 | 0 | 2 | 1 | 0 |
8181
+-----------------------+----------+------------+--------------+--------+
@@ -112,7 +112,7 @@ The following are available configurations for the testbench:
112112
-
113113
* -
114114
- CLK_MODE
115-
- NUM_OF_SDI
115+
- NUM_OF_SDIO
116116
- CAPTURE_ZONE
117117
- DDR_EN
118118
* - cfg_cm0_sdi2_cz1_ddr0

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