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LBFFilhoLBFFilho
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SPI Engine: improve instruction macros (#112)
Also get version from regmap Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
1 parent e34cce8 commit 51e772b

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3 files changed

+30
-25
lines changed

3 files changed

+30
-25
lines changed

‎common/sv/spi_engine_instr_pkg.sv‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
package spi_engine_instr_pkg;
22
// Chip select instructions
3-
`define INST_CS (32'h0000_1000)
4-
`define cs(mask) (`INST_CS | (mask & 8'hFF))
5-
`define cs_delay(m,d) (`INST_CS | ((d & 2'h3) << 8) | (m & 8'hFF))
6-
`define INST_CS_INV (32'h0000_4000)
7-
`define cs_inv_mask(m) (`INST_CS_INV | (m & 8'hFF))
3+
`define INST_CS (32'h0000_1000)
4+
`define SET_CS(b) (`INST_CS | (b & 8'hFF))
5+
`define SET_CS_DELAY(m,d) (`INST_CS | ((d & 2'h3) << 8) | (m & 8'hFF))
6+
`define INST_CS_INV (32'h0000_4000)
7+
`define SET_CS_INV_MASK(m) (`INST_CS_INV | (m & 8'hFF))
88

99
// Transfer instructions
1010
`define INST_WR (32'h0000_0100 | (`NUM_OF_WORDS-1))
@@ -15,12 +15,13 @@ package spi_engine_instr_pkg;
1515
`define INST_CFG (32'h0000_2100 | (`SDO_IDLE_STATE << 3) | (`THREE_WIRE << 2) | (`CPOL << 1) | `CPHA)
1616
`define INST_PRESCALE (32'h0000_2000 | `CLOCK_DIVIDER)
1717
`define INST_DLENGTH (32'h0000_2200 | `DATA_DLENGTH)
18+
`define SET_DLENGTH(d) (`INST_DLENGTH | (d & 8'hFF))
1819

1920
// Synchronization
2021
`define INST_SYNC (32'h0000_3000)
2122

2223
// Sleep instruction
2324
`define INST_SLEEP (32'h0000_3100)
24-
`define sleep(a) (`INST_SLEEP | (a & 8'hFF))
25+
`define SLEEP(a) (`INST_SLEEP | (a & 8'hFF))
2526

2627
endpackage

‎spi_engine/tests/test_program.sv‎

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,6 @@ import adi_spi_vip_pkg::*;
5252
//---------------------------------------------------------------------------
5353
// SPI Engine configuration parameters
5454
//---------------------------------------------------------------------------
55-
localparam PCORE_VERSION = 32'h0001_0300;
5655

5756
program test_program (
5857
inout spi_engine_irq,
@@ -160,7 +159,10 @@ end
160159
//---------------------------------------------------------------------------
161160

162161
task sanity_test();
163-
axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), PCORE_VERSION);
162+
bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH)
163+
| (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8
164+
| (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16;
165+
axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version);
164166
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF);
165167
axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF);
166168
`INFO(("Sanity Test Done"));
@@ -173,11 +175,11 @@ endtask
173175
task generate_transfer_cmd(
174176
input [7:0] sync_id);
175177
// assert CSN
176-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `cs(8'hFE));
178+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFE));
177179
// transfer data
178180
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_WRD);
179181
// de-assert CSN
180-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `cs(8'hFF));
182+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS(8'hFF));
181183
// SYNC command to generate interrupt
182184
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`INST_SYNC | sync_id));
183185
`INFOV(("Transfer generation finished."), 6);
@@ -255,11 +257,11 @@ task offload_spi_test();
255257
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_PRESCALE);
256258
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH);
257259
if (`CS_ACTIVE_HIGH) begin
258-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `cs_inv_mask(8'hFF));
260+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_INV_MASK(8'hFF));
259261
end
260-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `cs(8'hFE));
262+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFE));
261263
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_RD);
262-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `cs(8'hFF));
264+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFF));
263265
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2);
264266

265267
// Enqueue transfers to DUT
@@ -327,7 +329,7 @@ task fifo_spi_test();
327329
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE);
328330
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH);
329331
if (`CS_ACTIVE_HIGH) begin
330-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `cs_inv_mask(8'hFF));
332+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF));
331333
end
332334

333335
// Set up the interrupts

‎spi_engine/tests/test_sleep_delay.sv‎

Lines changed: 13 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,6 @@ import adi_spi_vip_pkg::*;
5050
//---------------------------------------------------------------------------
5151
// SPI Engine configuration parameters
5252
//---------------------------------------------------------------------------
53-
localparam PCORE_VERSION = 32'h0001_0300;
5453

5554
program test_sleep_delay (
5655
inout spi_engine_irq,
@@ -155,7 +154,10 @@ end
155154
//---------------------------------------------------------------------------
156155

157156
task sanity_test();
158-
axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), PCORE_VERSION);
157+
bit [31:0] pcore_version = (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_PATCH)
158+
| (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MINOR)<<8
159+
| (`DEFAULT_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR)<<16;
160+
axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_VERSION), pcore_version);
159161
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF);
160162
axi_read_v (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_SCRATCH), 32'hDEADBEEF);
161163
`INFO(("Sanity Test Done"));
@@ -296,14 +298,14 @@ task sleep_delay_test(
296298
// Write commands
297299
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_CFG);
298300
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_PRESCALE);
299-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), ((`INST_DLENGTH) & 32'hFFFF_FF00) | 16);
301+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_DLENGTH(`DATA_WIDTH - `DATA_DLENGTH));
300302
if (`CS_ACTIVE_HIGH) begin
301-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `cs_inv_mask(8'hFF));
303+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `SET_CS_INV_MASK(8'hFF));
302304
end
303305

304306
expected_sleep_time = 2+(sleep_param)*((`CLOCK_DIVIDER+1)*2);
305307
// Start the test
306-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`sleep(sleep_param)));
308+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`SLEEP(sleep_param)));
307309

308310
#2000ns
309311
sleep_time = sleep_instr_time.pop_back();
@@ -315,7 +317,7 @@ task sleep_delay_test(
315317

316318
// change the SPI word size (this should not affect sleep delay)
317319
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), `INST_DLENGTH);
318-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`sleep(sleep_param)));
320+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_CMD_FIFO), (`SLEEP(sleep_param)));
319321
#2000ns
320322
sleep_time = sleep_instr_time.pop_back();
321323
#100ns
@@ -382,11 +384,11 @@ task cs_delay_test(
382384
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_PRESCALE);
383385
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_DLENGTH);
384386
if (`CS_ACTIVE_HIGH) begin
385-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `cs_inv_mask(8'hFF));
387+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_INV_MASK(8'hFF));
386388
end
387-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `cs(8'hFE));
389+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFE));
388390
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_RD);
389-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `cs(8'hFF));
391+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS(8'hFF));
390392
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 1);
391393

392394
expected_cs_activate_time = 2;
@@ -443,9 +445,9 @@ task cs_delay_test(
443445

444446
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(1));
445447
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET), `SET_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(0));
446-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `cs_delay(8'hFE,cs_activate_delay));
448+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_DELAY(8'hFE,cs_activate_delay));
447449
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_RD);
448-
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `cs_delay(8'hFF,cs_deactivate_delay));
450+
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `SET_CS_DELAY(8'hFF,cs_deactivate_delay));
449451
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2);
450452

451453
// breakdown: cs_activate_delay*(1+`CLOCK_DIVIDER)*2, times 2 since it's before and after cs transition, and added 3 cycles (1 for each timer comparison, plus one for fetching next instruction)

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