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IstvanZsSzekelyIstvanZsSzekely
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util_axis_fifo: Initial testbench commit
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
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‎testbenches/ip/util_axis_fifo/Makefile‎

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####################################################################################
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####################################################################################
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## Copyright 2022(c) Analog Devices, Inc.
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####################################################################################
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####################################################################################
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# Makeincludes
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include ../../../scripts/make_tb_path.mk
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include $(TB_LIBRARY_PATH)/includes/Makeinclude_common.mk
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include $(TB_LIBRARY_PATH)/includes/Makeinclude_axis.mk
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include $(TB_LIBRARY_PATH)/includes/Makeinclude_scoreboard.mk
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# Remaining test-bench dependencies except test programs
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SV_DEPS += environment.sv
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LIB_DEPS := util_cdc
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LIB_DEPS += util_axis_fifo
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# default test program
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TP := test_program
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# config files should have the following format
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# cfg_<param1>_<param2>.tcl
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CFG_FILES := $(notdir $(wildcard cfgs/cfg*.tcl))
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#$(warning $(CFG_FILES))
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# List of tests and configuration combinations that has to be run
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# Format is: <configuration>:<test name>
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TESTS := $(foreach cfg, $(basename $(CFG_FILES)), $(cfg):$(TP))
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include ../../../scripts/project-sim.mk
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# usage :
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#
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# run specific test on a specific configuration in gui mode
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# make CFG=cfg2_fsync TST=test_frame_delay MODE=gui
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#
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# run all test from a configuration
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# make cfg1_mm2mm_default
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####################################################################################
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####################################################################################

‎testbenches/ip/util_axis_fifo/README.md‎

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Usage :
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Run all tests in batch mode:
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make
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Run all tests in GUI mode:
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make MODE=gui
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Run specific test on a specific configuration in gui mode:
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make CFG=<name of cfg> TST=<name of test> MODE=gui
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Run all test from a configuration:
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make <name of cfg>
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Where:
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* <name of cfg> is a file from the cfgs directory without the tcl extension of format cfg\*
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* <name of test> is a file from the tests directory without the tcl extension
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‎testbenches/ip/util_axis_fifo/cfgs/cfg_rand.tcl‎

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global ad_project_params
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set async_clk [expr int(rand()*2)]
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set ad_project_params(ASYNC_CLK) $async_clk
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set tkeep_en [expr int(rand()*2)]
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set ad_project_params(TKEEP_EN) $tkeep_en
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set tlast_en [expr int(rand()*2)]
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set ad_project_params(TLAST_EN) $tlast_en
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set random_width [expr int(8*pow(2, int(7.0*rand()+1)))]
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set DATA_WIDTH $random_width
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set ad_project_params(DATA_WIDTH) $DATA_WIDTH
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set random_width [expr int(5.0*rand())]
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set ad_project_params(ADDRESS_WIDTH) $random_width
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set input_clk [expr int(rand()*9)+1]
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set ad_project_params(INPUT_CLK) $input_clk
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if {$async_clk} {
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set output_clk [expr int(rand()*9)+1]
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set ad_project_params(OUTPUT_CLK) $output_clk
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} else {
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set ad_project_params(OUTPUT_CLK) $input_clk
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}

‎testbenches/ip/util_axis_fifo/environment.sv‎

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`include "utils.svh"
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`include "axis_definitions.svh"
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package environment_pkg;
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import logger_pkg::*;
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import adi_common_pkg::*;
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import axi4stream_vip_pkg::*;
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import m_axis_sequencer_pkg::*;
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import s_axis_sequencer_pkg::*;
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import adi_axis_agent_pkg::*;
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import scoreboard_pkg::*;
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class util_axis_fifo_environment #(`AXIS_VIP_PARAM_DECL(input_axis), `AXIS_VIP_PARAM_DECL(output_axis), int INPUT_CLK, int OUTPUT_CLK) extends adi_environment;
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virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(INPUT_CLK)) input_clk_vip_if;
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virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(OUTPUT_CLK)) output_clk_vip_if;
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adi_axis_master_agent #(`AXIS_VIP_PARAM_ORDER(input_axis)) input_axis_agent;
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adi_axis_slave_agent #(`AXIS_VIP_PARAM_ORDER(output_axis)) output_axis_agent;
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scoreboard #(logic [7:0]) scoreboard_inst;
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//============================================================================
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// Constructor
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//============================================================================
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function new (
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input string name,
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virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(INPUT_CLK)) input_clk_vip_if,
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virtual interface clk_vip_if #(.C_CLK_CLOCK_PERIOD(OUTPUT_CLK)) output_clk_vip_if,
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virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(input_axis)) input_axis_vip_if,
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virtual interface axi4stream_vip_if #(`AXIS_VIP_IF_PARAMS(output_axis)) output_axis_vip_if);
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// creating the agents
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super.new(name);
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this.input_clk_vip_if = input_clk_vip_if;
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this.output_clk_vip_if = output_clk_vip_if;
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this.input_axis_agent = new("Input AXI Stream Agent", input_axis_vip_if, this);
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this.output_axis_agent = new("Output AXI Stream Agent", output_axis_vip_if, this);
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this.scoreboard_inst = new("Util AXIS FIFO Scoreboard", this);
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endfunction
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//============================================================================
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// Configure environment
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//============================================================================
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task configure();
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// configuration for input
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this.input_axis_agent.sequencer.set_stop_policy(STOP_POLICY_PACKET);
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this.input_axis_agent.sequencer.set_data_gen_mode(DATA_GEN_MODE_AUTO_INCR);
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this.input_axis_agent.sequencer.set_descriptor_gen_mode(1);
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this.input_axis_agent.sequencer.set_data_beat_delay(0);
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this.input_axis_agent.sequencer.set_descriptor_delay(0);
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this.input_axis_agent.sequencer.set_inactive_drive_output_0();
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// configuration for output
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this.output_axis_agent.sequencer.set_mode(XIL_AXI4STREAM_READY_GEN_NO_BACKPRESSURE);
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// this.output_axis_agent.sequencer.set_use_variable_ranges();
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// this.output_axis_agent.sequencer.set_high_time_range(1,1);
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// this.output_axis_agent.sequencer.set_low_time_range(0,0);
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// this.output_axis_agent.sequencer.clr_use_variable_ranges();
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// this.output_axis_agent.sequencer.set_high_time(1);
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// this.output_axis_agent.sequencer.set_low_time(1);
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endtask
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//============================================================================
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// Start environment
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// - Connect all the agents to the scoreboard
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// - Start the agents
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//============================================================================
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task start();
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this.input_clk_vip_if.start_clock();
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this.output_clk_vip_if.start_clock();
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this.input_axis_agent.start();
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this.output_axis_agent.start();
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this.input_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_source);
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this.output_axis_agent.monitor.publisher.subscribe(this.scoreboard_inst.subscriber_sink);
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endtask
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//============================================================================
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// Run subroutine
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//============================================================================
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task run();
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fork
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this.input_axis_agent.run();
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this.output_axis_agent.run();
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this.scoreboard_inst.run();
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join_none
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endtask
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//============================================================================
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// Stop subroutine
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//============================================================================
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task stop();
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this.input_axis_agent.stop();
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this.output_axis_agent.stop();
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endtask
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endclass
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endpackage

‎testbenches/ip/util_axis_fifo/system_bd.tcl‎

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# ***************************************************************************
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# ***************************************************************************
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# Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
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#
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# In this HDL repository, there are many different and unique modules, consisting
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# of various HDL (Verilog or VHDL) components. The individual modules are
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# developed independently, and may be accompanied by separate and unique license
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# terms.
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#
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# The user should read each of these license terms, and understand the
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# freedoms and responsibilities that he or she has by using this source/core.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE.
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#
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# Redistribution and use of source or resulting binaries, with or without modification
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# of this file, are permitted under one of the following two license terms:
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#
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# 1. The GNU General Public License version 2 as published by the
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# Free Software Foundation, which can be found in the top level directory
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# of this repository (LICENSE_GPL2), and also online at:
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# <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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#
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# OR
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#
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# 2. An ADI specific BSD license, which can be found in the top level directory
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# of this repository (LICENSE_ADIBSD), and also on-line at:
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# https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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# This will allow to generate bit files and not release the source code,
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# as long as it attaches to an ADI device.
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#
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# ***************************************************************************
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# ***************************************************************************
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global ad_project_params
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set ASYNC_CLK $ad_project_params(ASYNC_CLK)
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set TKEEP_EN $ad_project_params(TKEEP_EN)
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set TLAST_EN $ad_project_params(TLAST_EN)
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set DATA_WIDTH $ad_project_params(DATA_WIDTH)
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set ADDRESS_WIDTH $ad_project_params(ADDRESS_WIDTH)
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set INPUT_CLK $ad_project_params(INPUT_CLK)
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set OUTPUT_CLK $ad_project_params(OUTPUT_CLK)
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# Input clock
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ad_ip_instance clk_vip input_clk_vip [ list \
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INTERFACE_MODE {MASTER} \
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FREQ_HZ [expr pow(10, 9)/$INPUT_CLK] \
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]
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adi_sim_add_define "INPUT_CLK_VIP=input_clk_vip"
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ad_ip_instance clk_vip output_clk_vip [ list \
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INTERFACE_MODE {MASTER} \
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FREQ_HZ [expr pow(10, 9)/$OUTPUT_CLK] \
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]
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adi_sim_add_define "OUTPUT_CLK_VIP=output_clk_vip"
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ad_connect input_clk input_clk_vip/clk_out
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ad_connect output_clk output_clk_vip/clk_out
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ad_ip_instance proc_sys_reset input_rstgen
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ad_ip_parameter input_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_ip_instance proc_sys_reset output_rstgen
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ad_ip_parameter output_rstgen CONFIG.C_EXT_RST_WIDTH 1
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ad_connect sys_rst_vip/rst_out input_rstgen/ext_reset_in
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ad_connect sys_rst_vip/rst_out output_rstgen/ext_reset_in
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ad_connect input_clk input_rstgen/slowest_sync_clk
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ad_connect output_clk output_rstgen/slowest_sync_clk
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ad_connect input_resetn input_rstgen/peripheral_aresetn
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ad_connect output_resetn output_rstgen/peripheral_aresetn
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ad_ip_instance util_axis_fifo util_axis_fifo_DUT [list \
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ASYNC_CLK $ASYNC_CLK \
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DATA_WIDTH $DATA_WIDTH \
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ADDRESS_WIDTH $ADDRESS_WIDTH \
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M_AXIS_REGISTERED 1 \
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ALMOST_EMPTY_THRESHOLD 0 \
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ALMOST_FULL_THRESHOLD 0 \
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TLAST_EN $TLAST_EN \
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TKEEP_EN $TKEEP_EN \
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REMOVE_NULL_BEAT_EN 0 \
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]
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ad_connect input_clk util_axis_fifo_DUT/s_axis_aclk
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ad_connect input_resetn util_axis_fifo_DUT/s_axis_aresetn
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ad_connect output_clk util_axis_fifo_DUT/m_axis_aclk
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ad_connect output_resetn util_axis_fifo_DUT/m_axis_aresetn
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ad_ip_instance axi4stream_vip input_axis [list \
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INTERFACE_MODE {MASTER} \
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HAS_TREADY {1} \
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TDEST_WIDTH {0} \
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TID_WIDTH {0} \
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HAS_TLAST $TLAST_EN \
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HAS_TKEEP $TKEEP_EN \
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TDATA_NUM_BYTES [expr {$DATA_WIDTH/8}] \
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]
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adi_sim_add_define "INPUT_AXIS=input_axis"
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ad_connect input_clk input_axis/aclk
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ad_connect input_resetn input_axis/aresetn
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ad_connect util_axis_fifo_DUT/s_axis input_axis/m_axis
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ad_ip_instance axi4stream_vip output_axis [list \
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INTERFACE_MODE {SLAVE} \
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HAS_TLAST $TLAST_EN \
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HAS_TKEEP $TKEEP_EN \
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TDATA_NUM_BYTES [expr {$DATA_WIDTH/8}] \
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]
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adi_sim_add_define "OUTPUT_AXIS=output_axis"
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ad_connect output_clk output_axis/aclk
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ad_connect output_resetn output_axis/aresetn
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ad_connect util_axis_fifo_DUT/m_axis output_axis/s_axis

‎testbenches/ip/util_axis_fifo/system_project.tcl‎

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source ../../../scripts/adi_sim.tcl
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if {$argc < 1} {
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puts "Expecting at least one argument that specifies the test configuration"
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exit 1
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} else {
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set cfg_file [lindex $argv 0]
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}
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# Read config file
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source "cfgs/${cfg_file}"
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# Set the project name
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set project_name [file rootname $cfg_file]
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# Create the project
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adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e"
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source $ad_tb_dir/library/includes/sp_include_axis.tcl
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source $ad_tb_dir/library/includes/sp_include_scoreboard.tcl
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# Add test files to the project
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adi_sim_project_files [list \
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"environment.sv" \
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"tests/test_program.sv" \
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]
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#set a default test program
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adi_sim_add_define "TEST_PROGRAM=test_program"
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adi_sim_generate $project_name

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