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docs: Scoreboard testbench
Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>
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.. _scoreboard_tb:
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Scoreboard
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================================================================================
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Overview
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-------------------------------------------------------------------------------
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The purpose of this testbench is to give engineers a sandbox testbench, where
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they can test the scoreboard's functionalities.
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Block design
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-------------------------------------------------------------------------------
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The block design is based on the test harness with the addition of two AXI4
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Stream VIPs from AMD. This testbench does not require the presence of the test
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harness, as it can work without it, but since it was created based on the base
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design, this was inherited. One of the VIPs is configured as master, while the
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other one is configured as slave. The TREADY, TLAST and TKEEP signals are set to
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be enabled for the VIPs.
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. image:: ../axis_sequencers/axis_sequencers_tb.svg
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:width: 800
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:align: center
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:alt: Scoreboard/Testbench block diagram
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Configuration parameters and modes
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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There are no parameters that can be configured in the testbench configuration
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files.
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Build parameters
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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There are no build parameters for this testbench.
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Configuration files
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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As this is a sandbox testbench, engineers are encouraged to change parameters
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and see what happens in the simulation. Since there are no parameters available
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for edit, the coniguration file's purpose is to give the testbench instance a
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name.
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Tests
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The following test program file is available:
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============ ==============================
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Test program Usage
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============ ==============================
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test_program Creates a basic test stimulus.
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============ ==============================
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Available configurations & tests combinations
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The test program is compatible with the configuration.
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Irrelevant for this testbench.
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Irrelevant for this testbench.
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Test stimulus
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-------------------------------------------------------------------------------
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The test program is responsible for configuring and running the sequencers,
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while checking the data with a scoreboard.
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Environment Bringup
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The steps of the environment bringup are:
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* Create the environment
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* Start the environment
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* Start the clocks
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* Assert the resets
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Scoreboard testing
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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* Before the resets are asserted, the master and slave sequencers are configured
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* The scoreboard is subscribed to the master and slave sequencers' publisher
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* The scoreboard is started
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* The sequencers are started
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* Scoreboard waits until the verification is complete
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.. warning::
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Depending on the packet size and amount, the simulation may end before all of
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the data is verified, which may cause runtime errors!
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Building the test bench
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-------------------------------------------------------------------------------
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The testbench is built upon ADI's generic HDL reference design framework.
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ADI does not distribute compiled files of these projects so they must be built
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from the sources available :git-hdl:`here </>` and :git-testbenches:`here </>`,
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with the specified hierarchy described :ref:`build_tb set_up_tb_repo`.
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To get the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:
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**Linux/Cygwin/WSL**
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*Example 1*
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Building and simulating the testbench using only the command line.
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.. shell::
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:showuser:
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$cd testbenches/ip/scoreboard
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$make
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*Example 2*
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Building and simulating the testbench using the Vivado GUI. This command will
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launch Vivado, will run the simulation and display the waveforms.
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.. shell::
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:showuser:
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$cd testbenches/ip/scoreboard
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$make MODE=gui
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*Example 3*
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Build a particular combination of test and configuration, using the Vivado GUI.
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This command will launch Vivado, will run the simulation and display the
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waveforms.
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.. shell::
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:showuser:
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$cd testbenches/ip/scoreboard
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$make MODE=gui CFG=cfg1 TST=test_program
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The built project can be found in the ``runs`` folder, where each configuration
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specific build has its own folder named after the configuration file's name.
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Example: if the following command was run for a single configuration in the
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clean folder (no runs folder available):
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``make CFG=cfg1``
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Then the subfolder under ``runs`` name will be:
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``cfg1``
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Resources
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-------------------------------------------------------------------------------
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Testbenches related dependencies
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. include:: ../../common/dependency_common.rst
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Testbench specific dependencies:
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.. list-table::
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:widths: 30 45 25
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:header-rows: 1
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* - SV dependency name
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- Source code link
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- Documentation link
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* - M_AXIS_SEQUENCER
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- :git-testbenches:`library/vip/amd/m_axis_sequencer.sv`
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- ---
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* - S_AXIS_SEQUENCER
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- :git-testbenches:`library/vip/amd/s_axis_sequencer.sv`
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- ---
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* - SCOREBOARD
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- :git-testbenches:`library/drivers/common/scoreboard.sv`
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- ---
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.. include:: ../../../common/more_information.rst
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.. include:: ../../../common/support.rst

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