scoreboard: Simplified to AXIS data packet verification

Signed-off-by: Istvan-Zsolt Szekely <istvan.szekely@analog.com>

Author: IstvanZsSzekely

library/drivers/common/scoreboard.sv

@@ -65,9 +65,7 @@ package scoreboard_pkg;
           this.byte_stream.push_back(data.pop_front());
         end
 
-        if (this.scoreboard_ref.get_enabled()) begin
-          this.scoreboard_ref.compare_transaction();
-        end
+        this.scoreboard_ref.compare_transaction();
       endfunction: update
 
       function data_type get_data();
@@ -121,7 +119,7 @@ package scoreboard_pkg;
     // run task
     task run();
       this.enabled = 1;
-
+      this.clear_streams();
       this.info($sformatf("Scoreboard enabled"), ADI_VERBOSITY_MEDIUM);
     endtask: run
 
@@ -132,10 +130,6 @@ package scoreboard_pkg;
       this.byte_streams_empty_sig = 1;
     endtask: stop
 
-    function bit get_enabled();
-      return this.enabled;
-    endfunction: get_enabled
-
     // set sink type
     function void set_sink_type(input bit sink_type);
       if (!this.enabled) begin
@@ -153,7 +147,7 @@ package scoreboard_pkg;
     // clear source and sink byte streams
     protected function void clear_streams();
       this.subscriber_source.clear_stream();
-      this.subscriber_source.clear_stream();
+      this.subscriber_sink.clear_stream();
     endfunction: clear_streams
 
     // wait until source and sink byte streams are empty, full check

testbenches/ip/scoreboard/Makefile

@@ -12,15 +12,6 @@ include $(TB_LIBRARY_PATH)/includes/Makeinclude_scoreboard.mk
 include $(TB_LIBRARY_PATH)/includes/Makeinclude_dmac.mk
 include $(TB_LIBRARY_PATH)/includes/Makeinclude_data_offload.mk
 
-# Remaining test-bench dependencies except test programs
-SV_DEPS += environment.sv
-
-LIB_DEPS := util_cdc
-LIB_DEPS += util_axis_fifo
-LIB_DEPS += axi_dmac
-LIB_DEPS += data_offload
-LIB_DEPS += util_do_ram
-
 # default test program
 TP := test_program
 

testbenches/ip/scoreboard/cfgs/cfg1.tcl

@@ -1,19 +1 @@
 global ad_project_params
-
-set ad_project_params(ADC_DATA_PATH_WIDTH)  16     ; ##
-set ad_project_params(DAC_DATA_PATH_WIDTH)  16     ; ##
-
-set ad_project_params(ADC_PATH_TYPE) 0             ; ## RX
-set ad_project_params(ADC_OFFLOAD_MEM_TYPE) 0      ; ## External storage
-set ad_project_params(ADC_OFFLOAD_SIZE) 2048       ; ## Storage size in bytes
-set ad_project_params(ADC_OFFLOAD_SRC_DWIDTH) 128  ; ## Source data width
-set ad_project_params(ADC_OFFLOAD_DST_DWIDTH) 128  ; ## Destination data width
-
-set ad_project_params(DAC_PATH_TYPE) 0             ; ## TX
-set ad_project_params(DAC_OFFLOAD_MEM_TYPE) 0      ; ## External storage
-set ad_project_params(DAC_OFFLOAD_SIZE) 2048       ; ## Storage size in bytes
-set ad_project_params(DAC_OFFLOAD_SRC_DWIDTH) 128  ; ## Source data width
-set ad_project_params(DAC_OFFLOAD_DST_DWIDTH) 128  ; ## Destination data width
-
-set ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH) 512      ; ## PLDDR's AXI4 interface data width
-

testbenches/ip/scoreboard/environment.sv

@@ -35,143 +35,28 @@
 
 global ad_project_params
 
-source "$ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl"
-
-## DUT configuration
-
-set adc_data_path_width $ad_project_params(ADC_DATA_PATH_WIDTH)
-set dac_data_path_width $ad_project_params(DAC_DATA_PATH_WIDTH)
-
-set adc_path_type $ad_project_params(ADC_PATH_TYPE)
-set adc_offload_mem_type $ad_project_params(ADC_OFFLOAD_MEM_TYPE)
-set adc_offload_size $ad_project_params(ADC_OFFLOAD_SIZE)
-set adc_offload_src_dwidth $ad_project_params(ADC_OFFLOAD_SRC_DWIDTH)
-set adc_offload_dst_dwidth $ad_project_params(ADC_OFFLOAD_DST_DWIDTH)
-
-set dac_path_type $ad_project_params(DAC_PATH_TYPE)
-set dac_offload_mem_type $ad_project_params(DAC_OFFLOAD_MEM_TYPE)
-set dac_offload_size $ad_project_params(DAC_OFFLOAD_SIZE)
-set dac_offload_src_dwidth $ad_project_params(DAC_OFFLOAD_SRC_DWIDTH)
-set dac_offload_dst_dwidth $ad_project_params(DAC_OFFLOAD_DST_DWIDTH)
-
-set plddr_offload_data_width $ad_project_params(PLDDR_OFFLOAD_DATA_WIDTH)
-
-ad_ip_instance xlconstant GND [list \
-  CONST_VAL 0 \
+ad_ip_instance axi4stream_vip adc_src_axis [list \
+  INTERFACE_MODE {MASTER} \
+  TDATA_NUM_BYTES 2 \
+  HAS_TREADY {1} \
+  HAS_TKEEP {1} \
+  HAS_TLAST {1} \
 ]
-ad_connect gnd GND/dout
-
-for {set i 0} {$i < 2} {incr i} {
-  ad_ip_instance axi_dmac i_rx_dmac_${i} [list \
-    DMA_TYPE_SRC 1 \
-    DMA_TYPE_DEST 0 \
-    ID 0 \
-    AXI_SLICE_SRC 1 \
-    AXI_SLICE_DEST 1 \
-    SYNC_TRANSFER_START 0 \
-    DMA_LENGTH_WIDTH 24 \
-    DMA_2D_TRANSFER 0 \
-    MAX_BYTES_PER_BURST 4096 \
-    CYCLIC 0 \
-    DMA_DATA_WIDTH_SRC $adc_offload_dst_dwidth \
-    DMA_DATA_WIDTH_DEST 64 \
-  ]
-
-  ad_ip_instance axi_dmac i_tx_dmac_${i} [list \
-    DMA_TYPE_SRC 0 \
-    DMA_TYPE_DEST 1 \
-    ID 0 \
-    AXI_SLICE_SRC 1 \
-    AXI_SLICE_DEST 1 \
-    SYNC_TRANSFER_START 0 \
-    DMA_LENGTH_WIDTH 24 \
-    DMA_2D_TRANSFER 0 \
-    MAX_BYTES_PER_BURST 4096 \
-    CYCLIC 1 \
-    DMA_DATA_WIDTH_SRC 64 \
-    DMA_DATA_WIDTH_DEST $dac_offload_src_dwidth \
-  ]
-
-  ad_data_offload_create RX_DUT_${i} \
-                         0 \
-                         $adc_offload_mem_type \
-                         $adc_offload_size \
-                         $adc_offload_src_dwidth \
-                         $adc_offload_dst_dwidth \
-                         $plddr_offload_data_width
-
-  ad_data_offload_create TX_DUT_${i} \
-                         1 \
-                         $dac_offload_mem_type \
-                         $dac_offload_size \
-                         $dac_offload_src_dwidth \
-                         $dac_offload_dst_dwidth \
-                         $plddr_offload_data_width
-
-  set BA 0x50000000
-  ad_cpu_interconnect [expr ${BA} + 0x00000 + $i*0x40000] i_rx_dmac_${i}
-  ad_cpu_interconnect [expr ${BA} + 0x10000 + $i*0x40000] i_tx_dmac_${i}
-  ad_cpu_interconnect [expr ${BA} + 0x20000 + $i*0x40000] RX_DUT_${i}
-  ad_cpu_interconnect [expr ${BA} + 0x30000 + $i*0x40000] TX_DUT_${i}
-
-  adi_sim_add_define "RX_DMA_BA_${i}=[format "%d" [expr ${BA} + 0x00000 + $i*0x40000]]"
-  adi_sim_add_define "TX_DMA_BA_${i}=[format "%d" [expr ${BA} + 0x10000 + $i*0x40000]]"
-  adi_sim_add_define "RX_DOFF_BA_${i}=[format "%d" [expr ${BA} + 0x20000 + $i*0x40000]]"
-  adi_sim_add_define "TX_DOFF_BA_${i}=[format "%d" [expr ${BA} + 0x30000 + $i*0x40000]]"
+adi_sim_add_define "ADC_SRC_AXIS=adc_src_axis"
 
-  ad_ip_instance axi4stream_vip adc_src_axis_${i} [list \
-    INTERFACE_MODE {MASTER} \
-    HAS_TREADY {1} \
-    HAS_TLAST {0} \
-    TDATA_NUM_BYTES $adc_data_path_width \
-  ]
-  adi_sim_add_define "ADC_SRC_AXIS_${i}=adc_src_axis_${i}"
+ad_connect sys_dma_clk adc_src_axis/aclk
+ad_connect sys_dma_resetn adc_src_axis/aresetn
 
-  ad_connect adc_src_axis_${i}/m_axis RX_DUT_${i}/s_axis
-  ad_connect RX_DUT_${i}/m_axis i_rx_dmac_${i}/s_axis
-
-  ad_connect sys_dma_clk adc_src_axis_${i}/aclk
-  ad_connect sys_dma_resetn adc_src_axis_${i}/aresetn
-
-  ad_connect sys_dma_clk RX_DUT_${i}/s_axis_aclk
-  ad_connect sys_dma_resetn RX_DUT_${i}/s_axis_aresetn
-  ad_connect sys_cpu_clk RX_DUT_${i}/m_axis_aclk
-  ad_connect sys_cpu_resetn RX_DUT_${i}/m_axis_aresetn
-
-  ad_connect sys_cpu_clk i_rx_dmac_${i}/s_axis_aclk
-  ad_connect sys_mem_clk i_rx_dmac_${i}/m_dest_axi_aclk
-  ad_connect sys_mem_resetn i_rx_dmac_${i}/m_dest_axi_aresetn
-
-  ad_connect i_rx_dmac_${i}/s_axis_xfer_req RX_DUT_${i}/init_req
-  ad_connect gnd RX_DUT_${i}/sync_ext
-
-  ad_mem_hp0_interconnect sys_mem_clk i_rx_dmac_${i}/m_dest_axi
-
-  ad_ip_instance axi4stream_vip dac_dst_axis_${i} [list \
-    INTERFACE_MODE {SLAVE} \
-    TDATA_NUM_BYTES $dac_data_path_width \
-    HAS_TLAST {1} \
-    HAS_TKEEP {0} \
-  ]
-  adi_sim_add_define "DAC_DST_AXIS_${i}=dac_dst_axis_${i}"
-
-  ad_connect sys_dma_clk dac_dst_axis_${i}/aclk
-  ad_connect sys_dma_resetn dac_dst_axis_${i}/aresetn
-
-  ad_connect sys_dma_clk TX_DUT_${i}/m_axis_aclk
-  ad_connect sys_dma_resetn TX_DUT_${i}/m_axis_aresetn
-  ad_connect sys_cpu_clk TX_DUT_${i}/s_axis_aclk
-  ad_connect sys_cpu_resetn TX_DUT_${i}/s_axis_aresetn
-
-  ad_connect sys_cpu_clk i_tx_dmac_${i}/m_axis_aclk
-  ad_connect sys_mem_clk i_tx_dmac_${i}/m_src_axi_aclk
-  ad_connect sys_mem_resetn i_tx_dmac_${i}/m_src_axi_aresetn
-
-  ad_connect TX_DUT_${i}/m_axis dac_dst_axis_${i}/s_axis
-  ad_connect TX_DUT_${i}/s_axis i_tx_dmac_${i}/m_axis
+ad_ip_instance axi4stream_vip dac_dst_axis [list \
+  INTERFACE_MODE {SLAVE} \
+  TDATA_NUM_BYTES 2 \
+  HAS_TREADY {1} \
+  HAS_TKEEP {1} \
+  HAS_TLAST {1} \
+]
+adi_sim_add_define "DAC_DST_AXIS=dac_dst_axis"
 
-  ad_connect i_tx_dmac_${i}/m_axis_xfer_req TX_DUT_${i}/init_req
-  ad_connect gnd TX_DUT_${i}/sync_ext
+ad_connect sys_dma_clk dac_dst_axis/aclk
+ad_connect sys_dma_resetn dac_dst_axis/aresetn
 
-  ad_mem_hp0_interconnect sys_mem_clk i_tx_dmac_${i}/m_src_axi
-}
+ad_connect adc_src_axis/m_axis dac_dst_axis/s_axis

testbenches/ip/scoreboard/system_bd.tcl

@@ -18,12 +18,9 @@ adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e"
 
 source $ad_tb_dir/library/includes/sp_include_axis.tcl
 source $ad_tb_dir/library/includes/sp_include_scoreboard.tcl
-source $ad_tb_dir/library/includes/sp_include_dmac.tcl
-source $ad_tb_dir/library/includes/sp_include_data_offload.tcl
 
 # Add test files to the project
 adi_sim_project_files [list \
-  "environment.sv" \
   "tests/test_program.sv" \
 ]