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@rroohhh rroohhh commented Oct 7, 2024

Do not infer the ports from the publicly accessible wires, but instead delegate finding the ports to the rtlil.convert function

Do not infer the ports from the publicly accessible wires, but instead delegate finding the
ports to the `rtlil.convert` function
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LGTM. Have you been using the RPC functionality?

@whitequark whitequark added this pull request to the merge queue Oct 7, 2024
Merged via the queue into amaranth-lang:main with commit 369dc19 Oct 7, 2024
@rroohhh rroohhh deleted the component_rpc branch October 7, 2024 22:01
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rroohhh commented Oct 7, 2024

Yeah I started using it for my current project, that requires a (system)verilog toplevel and also uses other preexisting non-amaranth modules.

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