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tests: examples: Add an RTL/UMI example
Signed-off-by: Edgar E. Iglesias <edgar@zeroasic.com>
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‎tests/Makefile‎

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SUBDIRS_EXAMPLES += example-rtl-axi4
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SUBDIRS_EXAMPLES += example-rtl-axi4lite
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SUBDIRS_EXAMPLES += example-rtl-mixed
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SUBDIRS_EXAMPLES += example-rtl-umi
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SUBDIRS += $(SUBDIRS_EXAMPLES)
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SUBDIRS += tlm-modules

‎tests/example-rtl-umi/Makefile‎

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#
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# Copyright (c) 2024 Zero ASIC.
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# Written by Edgar E. Iglesias.
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#
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# SPDX-License-Identifier: MIT
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#
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-include ../../.config.mk
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include ../Rules.mk
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UMI_DIR = ../../submodules/umi
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# Create a SystemC executable
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VFLAGS = -exe -sc -build
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VFLAGS += -Wall -Wno-fatal --pins-bv 2
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VFLAGS += --trace
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VFLAGS += -y $(UMI_DIR)/umi/rtl/
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VFLAGS += -y $(UMI_DIR)/submodules/lambdalib/ramlib/rtl/
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VFLAGS += -y $(UMI_DIR)/submodules/lambdalib/stdlib/rtl/
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CPPFLAGS += -I ../../../ -I ../../ -I .
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CXXFLAGS += -Wall -O3 -g
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ALL_OBJS += $(EXAMPLE_RTL_UMI_OBJS)
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VFILES = umi_dev.v
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SCFILES = example-rtl-umi.cc ../../trace/trace.cc
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# Conditionalize build on having the UMI submodule.
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ifeq ($(shell test -d $(UMI_DIR) && echo -n yes),yes)
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TARGETS += $(VOBJ_DIR)/example-rtl-umi
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endif
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all: $(TARGETS)
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.PHONY: $(VOBJ_DIR)/example-rtl-umi
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$(VOBJ_DIR)/example-rtl-umi:
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verilator -CFLAGS "$(CPPFLAGS)" $(VFLAGS) $(SCFILES) $(VFILES) -o example-rtl-umi
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clean:
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$(RM) -r $(VOBJ_DIR)
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$(RM) $(TARGETS:=.vcd)

‎tests/example-rtl-umi/example-rtl-umi.cc‎

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/*
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* This is a small example showing howto connect an RTL UMI Device
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* to a SystemC/TLM simulation using the TLM-2-UMI bridge.
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*
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* Copyright (c) 2024 Zero ASIC.
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* Written by Edgar E. Iglesias
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*
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* SPDX-License-Identifier: MIT
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*/
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#include <sstream>
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include "systemc"
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using namespace sc_core;
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using namespace sc_dt;
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using namespace std;
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#include "tlm.h"
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#include "tlm_utils/simple_initiator_socket.h"
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#include "tlm_utils/simple_target_socket.h"
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#include "tlm-bridges/tlm2umi-bridge.h"
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#include "traffic-generators/tg-tlm.h"
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#include "traffic-generators/traffic-desc.h"
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#include "test-modules/signals-umi.h"
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#include "test-modules/utils.h"
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#include "trace/trace.h"
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#if VM_TRACE
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#include <verilated_vcd_sc.h>
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#endif
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#include "Vumi_dev.h"
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using namespace utils;
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#define DW 64
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#define CONNECT_DUT(DUT, SIGS, SIGNAME) DUT.s00_axi_ ## SIGNAME(SIGS.SIGNAME)
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TrafficDesc transactions(merge({
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// Write something to address 8
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Write(8, DATA(0x1, 0x2, 0x3, 0x4)),
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// Read it back and check that we get the expected data.
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Read(8, 4),
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Expect(DATA(0x1, 0x2, 0x3, 0x4), 4)
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}));
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// Top simulation module.
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SC_MODULE(Top)
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{
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sc_clock clk;
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sc_signal<bool> rst;
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TLMTrafficGenerator tg;
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UMISignals<DW> signals_req;
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UMISignals<DW> signals_resp;
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tlm2umi_bridge<DW> bridge;
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Vumi_dev dut;
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void do_reset(void) {
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int i;
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rst.write(false);
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for (i = 0; i < 2; i++) {
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wait(clk.posedge_event());
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}
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rst.write(true);
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for (i = 0; i < 4; i++) {
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wait(clk.posedge_event());
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}
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rst.write(false);
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}
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SC_HAS_PROCESS(Top);
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Top(sc_module_name name) :
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clk("clk", sc_time(1, SC_US)),
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rst("rst"),
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tg("traffic_generator"),
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signals_req("signals_req"),
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signals_resp("signals_resp"),
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bridge("bridge"),
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dut("dut")
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{
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SC_THREAD(do_reset);
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// Configure the Traffic generator.
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tg.setStartDelay(sc_time(8, SC_US));
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tg.enableDebug();
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tg.addTransfers(transactions);
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tg.socket.bind(bridge.socket);
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// Wire up the clock and reset signals.
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bridge.clk(clk);
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bridge.rst(rst);
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dut.clk(clk);
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dut.rst(rst);
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// Wire-up the bridge and checker.
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signals_req.connect(bridge, "req_");
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signals_resp.connect(bridge, "resp_");
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signals_req.connect(dut, "udev_req_");
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signals_resp.connect(dut, "udev_resp_");
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}
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};
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int sc_main(int argc, char *argv[])
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{
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Top top("Top");
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#if VM_TRACE
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// Before any evaluation, need to know to calculate those signals only used for tracing
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Verilated::traceEverOn(true);
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#endif
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Verilated::commandArgs(argc, argv);
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// You must do one evaluation before enabling waves, in order to allow
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// SystemC to interconnect everything for testing.
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sc_start(SC_ZERO_TIME);
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sc_trace_file *trace_fp = sc_create_vcd_trace_file(argv[0]);
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trace(trace_fp, top, "top");
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#if VM_TRACE
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// General logfile
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ios::sync_with_stdio();
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// If verilator was invoked with --trace argument,
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// and if at run time passed the +trace argument, turn on tracing
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VerilatedVcdSc* tfp = nullptr;
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const char* flag = Verilated::commandArgsPlusMatch("trace");
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if (flag && 0 == std::strcmp(flag, "+trace")) {
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std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
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tfp = new VerilatedVcdSc;
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top.dut.trace(tfp, 99); // Trace 99 levels of hierarchy
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Verilated::mkdir("logs");
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tfp->open("logs/vlt_dump.vcd");
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trace_fp = sc_create_vcd_trace_file(argv[0]);
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trace(trace_fp, top, "Top");
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}
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#endif
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sc_start(140, SC_US);
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sc_stop();
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#if VM_TRACE
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// Flush the wave files each cycle so we can immediately see the output
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// Don't do this in "real" programs, do it in an abort() handler instead
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if (tfp) tfp->flush();
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#endif
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if (trace_fp) {
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sc_close_vcd_trace_file(trace_fp);
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}
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return 0;
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}

‎tests/example-rtl-umi/umi_dev.v‎

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/*
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* Wrapper around the UMI memory agent.
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*
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* Copyright (c) 2024 Zero ASIC.
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* Written by Edgar E. Iglesias
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*
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* SPDX-License-Identifier: MIT
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*/
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module umi_dev
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#(
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parameter DW = 64,
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parameter AW = 64
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)(
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input clk,
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input rst,
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input [31:0] udev_req_cmd,
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input [AW-1:0] udev_req_dstaddr,
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input [AW-1:0] udev_req_srcaddr,
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input [DW-1:0] udev_req_data,
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input udev_req_valid,
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output reg udev_req_ready,
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output reg [31:0] udev_resp_cmd,
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output reg [AW-1:0] udev_resp_dstaddr,
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output reg [AW-1:0] udev_resp_srcaddr,
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output reg [DW-1:0] udev_resp_data,
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output reg udev_resp_valid,
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input udev_resp_ready
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);
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wire nreset = ~rst;
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// See: submodules/umi/umi/rtl/umi_mem_agent.v
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wire [0:0] sram_ctrl;
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umi_mem_agent #(.AW(AW), .DW(DW), .CTRLW(1)) mem(.*);
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endmodule

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