[FEATURE] Implement generic function resolution for unconstrained generic type parameters

[nselvara]

This feature request stems from #389 and the provided #389 (comment).

---

Description

Currently, VHDL LS does not appear to support resolution function matching for generic function parameters of generic packages.

As described in the referenced discussion, this feature allows the compiler to automatically resolve and bind a function signature when a package is instantiated, if the generic function declaration includes an unconstrained signature (<>).

This mechanism is described in the LRM (e.g., Renerta reference - VHDL Generic Function Resolution, where a resolution function can be applied automatically when a function or subtype is generic over a type or function.

---

Example

library ieee;
use ieee.std_logic_1164.all;

package dummy_pkg is
  generic (
    type pkg_t;
    function to_string(p : pkg_t) return string is <>
  );
end package;

package body dummy_pkg is
end package;

package my_pkg is new dummy_pkg
  generic map (
    pkg_t => std_ulogic
  );

This works correctly in ModelSim, Riviera-PRO, and other compliant tools, but currently leads to unresolved or unrecognised generic function references in VHDL LS.

---

Suggestion

We could introduce automatic resolution function inference for unconstrained generic functions in VHDL LS analysis, following the same mechanism outlined in the VHDL LRM §4.6.2.3:

If a generic function parameter is declared with an unconstrained signature (is <>), the tool should attempt to match and bind it against visible functions in the scope during package instantiation.

This would make VHDL LS's behaviour consistent with other major simulators and improve code intelligence for modern VHDL-2008/2019 constructs.

---

References

• [BUG/CLARIFICATION/FEATURE] Record as generic type triggers mismatched_kinds error despite valid VHDL #389
• Stack Overflow: Can the VHDL 'image' attribute be invoked on a generic type?
• Renerta: VHDL Resolution Function Reference