[BUG] multiple generic package instantiation causes vhdl_ls to get confused.

[CheezuzCrust]

example with error as a comment in the file (modelsim compiles this code successfully)

library ieee;
use ieee.std_logic_1164.all;

package generic_record_pkg is
   generic(
      g_length : natural
   );

   type generic_record is record
      field: std_logic_vector(g_length-1 downto 0);
   end record;
end package;

library ieee;
use ieee.std_logic_1164.all;

entity tb_playground is
end entity;

use lib_playground.generic_record_pkg;

architecture arch of tb_playground is
   package i_gen_rec_pkg is new generic_record_pkg generic map(2);
   alias gen_rec_2 is i_gen_rec_pkg.generic_record;

   package i_other_gen_rec_pkg is new generic_record_pkg generic map(3);
   alias gen_rec_3 is i_other_gen_rec_pkg.generic_record; -- VHDL_LS message : "Duplicate Declaration of '"/="' with signature [generic_record, generic_record return BOOLEAN]
begin

end architecture;