"Found no match for operator" error on logical operations on arrays

[thoste]

Hi,
I've found an issue where you get the "Found no match for operator" error if you have logical operations on arrays.
This sould be valid code in VHDL.

Code example:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity foo is

end entity foo;

architecture rtl of foo is
   type t_bool_array is array (natural range <>) of boolean;

   signal result  : t_bool_array(3 downto 0);
   signal a_array : t_bool_array(3 downto 0);
   signal b_array : t_bool_array(3 downto 0);
begin

   result <= a_array or b_array;
   result <= a_array and b_array;

end architecture;

[JHertz5]

Hi @thoste. Can you elaborate on why you believe this code to be valid? The error looks legitimate to me. You have created a new type and have not defined the or operator for the new type.

You could get around this in this instance by using the built-in VHDL-2008 type boolean_vector instead of your custom type. The definition of the types are the same, but boolean_vector is built in to the language and comes with the various operators already defined for it.

I've had a go with your code example and when I change the type to a built-in type that has a definition for the or operator elsewhere, the errors go away.

[thoste]

Thank you @JHertz5,
Swapping our the custom type to the build in VHDL-2008 type made the error go away.

I found this when editing some older modules that were written with VHDL-93, hence the custom type.
And I meant that this was valid code because it can be compiled and synthesized with correct behaviour in hardware, so I though the language server could understand it too.
But I guess there is no parsing in the language server outside the built in types?