Reorganize RDLCompiler.elaborate() to make it easier to profile

Author: amykyta3

src/systemrdl/compiler.py

@@ -328,6 +328,21 @@ def elaborate(self, top_def_name: Optional[str]=None, inst_name: Optional[str]=N
             else:
                 self.msg.fatal("Could not find any 'addrmap' components to elaborate")
 
+        # Create design instance
+        root_node = self._elab_create_root_inst(top_def, inst_name, top_def_name, parameters)
+
+        # Elaborate the design
+        self._elab_design(root_node)
+
+        # Validate design
+        self._elab_validate(root_node)
+
+        if self.msg.had_error:
+            self.msg.fatal("Elaborate aborted due to previous errors")
+
+        return root_node
+
+    def _elab_create_root_inst(self, top_def: comp.Addrmap, inst_name: Optional[str], top_def_name: Optional[str], parameters: Dict[str, 'RDLValue']) -> RootNode:
         # Create an instance of the root component
         root_inst = self.root._copy_for_inst({}, recursive=True)
         root_inst.is_instance = True
@@ -370,6 +385,9 @@ def elaborate(self, top_def_name: Optional[str]=None, inst_name: Optional[str]=N
 
         root_node = RootNode(root_inst, self.env, None)
 
+        return root_node
+
+    def _elab_design(self, root_node: RootNode) -> None:
         # Resolve all expressions
         walker.RDLSimpleWalker(skip_not_present=False).walk(
             root_node,
@@ -388,14 +406,10 @@ def elaborate(self, top_def_name: Optional[str]=None, inst_name: Optional[str]=N
         # re-visit nodes a 2nd time as-needed to complete elaboration
         LateElabRevisitor(late_elab_listener.node_needs_revisit)
 
-        # Validate design
+    def _elab_validate(self, root_node: RootNode) -> None:
         # Only need to validate nodes that are present
         walker.RDLSimpleWalker(skip_not_present=True).walk(root_node, ValidateListener(self.env))
 
-        if self.msg.had_error:
-            self.msg.fatal("Elaborate aborted due to previous errors")
-
-        return root_node
 
 
     def eval(self, expression: str) ->'RDLValue':

test/benchmark/profile_rdl.py

@@ -25,9 +25,24 @@ def code_to_profile():
 profiler.bind_timer("systemrdl.preprocessor", "preprocess_file", "preprocess")
 profiler.bind_timer("systemrdl.parser.sa_systemrdl", "parse", "lex/parse")
 profiler.bind_timer("systemrdl.core.ComponentVisitor", "RootVisitor.visitRoot", "compile")
-profiler.bind_timer("systemrdl.compiler", "RDLCompiler.elaborate", "elaborate")
-
-profiler.bind_timer("systemrdl.component", "Component._copy_for_inst", "comp deepcopies")
+profiler.bind_timer("systemrdl.compiler", "RDLCompiler.elaborate", "elaborate total")
+profiler.bind_timer("systemrdl.compiler", "RDLCompiler._elab_create_root_inst", "elaborate-inst")
+profiler.bind_timer("systemrdl.compiler", "RDLCompiler._elab_design", "elaborate-expr")
+profiler.bind_timer("systemrdl.compiler", "RDLCompiler._elab_validate", "validate")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.enter_Component"            , "validate:enter_Component           ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.enter_Signal"               , "validate:enter_Signal              ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.enter_AddressableComponent" , "validate:enter_AddressableComponent")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.enter_Addrmap"              , "validate:enter_Addrmap             ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.enter_Reg"                  , "validate:enter_Reg                 ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.exit_Reg"                   , "validate:exit_Reg                  ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.enter_Field"                , "validate:enter_Field               ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.exit_Field"                 , "validate:exit_Field                ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.exit_Regfile"               , "validate:exit_Regfile              ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.exit_Addrmap"               , "validate:exit_Addrmap              ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.exit_Mem"                   , "validate:exit_Mem                  ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.exit_AddressableComponent"  , "validate:exit_AddressableComponent ")
+#profiler.bind_timer("systemrdl.core.validate", "ValidateListener.exit_Component"             , "validate:exit_Component            ")
+#profiler.bind_timer("systemrdl.node", "Node.get_property" , "Node.get_property")
 
 # Run!
 code_to_profile()