Add Node utilities for querying overlapping registers and fields

amykyta3 · amykyta3 · commit 723afcd07640 · 2025-11-15T10:25:18.000-08:00
diff --git a/src/systemrdl/component.py b/src/systemrdl/component.py
@@ -387,6 +387,19 @@ class Signal_PreStructuralElab(Signal):
 class Field(VectorComponent):
     original_def: Optional['Field']
 
+    def __init__(self) -> None:
+        super().__init__()
+
+        # List of field inst names that validly overlap (ro + wo) with this
+        # field. This is a list since it is theoretically possible for a wide
+        # field to overlap with multiple narrow fields.
+        self.overlaps_with_names: List[str] = []
+
+    def _copy_for_inst(self: 'Field', memo: Dict[int, Any], recursive: bool = False) -> 'Field':
+        result = super()._copy_for_inst(memo, recursive)
+        result.overlaps_with_names = copy(self.overlaps_with_names)
+        return result
+
 class Field_PreStructuralElab(Field):
     """
     Alternately typed representation for type hinting prior to structural placement
@@ -414,6 +427,11 @@ def __init__(self) -> None:
         # so names are unambiguous
         self._alias_names: List[str] = []
 
+        # List of register inst names that validly overlap (ro + wo) with this
+        # register. This is a list since it is theoretically possible for a wide
+        # register to overlap with multiple narrow registers.
+        self.overlaps_with_names: List[str] = []
+
         #------------------------------
         # Alias Register
         #------------------------------
@@ -428,6 +446,7 @@ def _copy_for_inst(self: 'Reg', memo: Dict[int, Any], recursive: bool = False) -
         result = super()._copy_for_inst(memo, recursive)
         result.is_msb0_order = self.is_msb0_order
         result._alias_names = copy(self._alias_names)
+        result.overlaps_with_names = copy(self.overlaps_with_names)
         result.is_alias = self.is_alias
         result.alias_primary_inst = deepcopy(self.alias_primary_inst, memo)
         return result
diff --git a/src/systemrdl/core/validate.py b/src/systemrdl/core/validate.py
@@ -96,6 +96,11 @@ def enter_AddressableComponent(self, node: AddressableNode) -> None:
                     ):
                         overlap_allowed = True
 
+                        # Stash information about overlaps so that it can be queried in the API
+                        node.inst.overlaps_with_names.append(prev_addressable.inst_name)
+                        prev_addressable.inst.overlaps_with_names.append(node.inst_name)
+
+
                 # Bridge addrmaps allow overlapping children
                 if isinstance(node.parent, AddrmapNode) and node.parent.get_property('bridge'):
                     overlap_allowed = True
@@ -367,14 +372,20 @@ def enter_Field(self, node: FieldNode) -> None:
                 # Check if the overlap is allowed
                 prev_f_sw = prev_field.get_property('sw')
 
-                if((prev_f_sw == rdltypes.AccessType.r)
-                    and (this_f_sw in (rdltypes.AccessType.w, rdltypes.AccessType.w1))
-                ):
-                    pass
-                elif((this_f_sw == rdltypes.AccessType.r)
-                    and (prev_f_sw in (rdltypes.AccessType.w, rdltypes.AccessType.w1))
+                if(
+                    (
+                        (prev_f_sw == rdltypes.AccessType.r)
+                        and (this_f_sw in {rdltypes.AccessType.w, rdltypes.AccessType.w1})
+                    )
+                    or (
+                        (this_f_sw == rdltypes.AccessType.r)
+                        and (prev_f_sw in {rdltypes.AccessType.w, rdltypes.AccessType.w1})
+                    )
                 ):
-                    pass
+                    # read-only + write-only overlap is OK
+                    # Stash information about overlaps so that it can be queried in the API
+                    node.inst.overlaps_with_names.append(prev_field.inst_name)
+                    prev_field.inst.overlaps_with_names.append(node.inst_name)
                 else:
                     self.msg.error(
                         "Field '%s[%d:%d]' overlaps with field '%s[%d:%d]'"
diff --git a/src/systemrdl/node.py b/src/systemrdl/node.py
@@ -2005,6 +2005,31 @@ def aliases(self, skip_not_present: bool = True) -> List['FieldNode']:
             fields.append(alias_field)
         return fields
 
+    @property
+    def has_overlaps(self) -> bool:
+        """
+        Returns True if this field overlaps with any other fields
+        that are present in the same register.
+
+        This is allowed if one is read-only and the other is write-only.
+
+
+        .. versionadded:: 1.31
+        """
+        return bool(self.inst.overlaps_with_names)
+
+    @property
+    def overlapping_fields(self) -> List['FieldNode']:
+        """
+        Returns a list of all other fields that overlap with this field.
+        """
+        fields = []
+        for field_name in self.inst.overlaps_with_names:
+            field = self.parent.get_child_by_name(field_name)
+            assert isinstance(field, FieldNode)
+            fields.append(field)
+        return fields
+
 
 #===============================================================================
 class RegNode(AddressableNode):
@@ -2300,7 +2325,7 @@ def has_aliases(self) -> bool:
 
     def aliases(self, skip_not_present: bool = True) -> List['RegNode']:
         """
-        Returns a listof all the registers that are aliases of this primary register
+        Returns a list of all the registers that are aliases of this primary register
 
         Parameters
         ----------
@@ -2329,6 +2354,30 @@ def aliases(self, skip_not_present: bool = True) -> List['RegNode']:
             regs.append(alias_reg)
         return regs
 
+    @property
+    def has_overlaps(self) -> bool:
+        """
+        Returns True if this register overlaps with any other registers
+        that are present in the design.
+
+        This is allowed if one is read-only and the other is write-only.
+
+
+        .. versionadded:: 1.31
+        """
+        return bool(self.inst.overlaps_with_names)
+
+    @property
+    def overlapping_regs(self) -> List['RegNode']:
+        """
+        Returns a list of all other registers that overlap with this register.
+        """
+        regs = []
+        for reg_name in self.inst.overlaps_with_names:
+            reg = self.parent.get_child_by_name(reg_name)
+            assert isinstance(reg, RegNode)
+            regs.append(reg)
+        return regs
 
 
 
diff --git a/test/rdl_src/overlaps.rdl b/test/rdl_src/overlaps.rdl
@@ -0,0 +1,84 @@
+addrmap top {
+    field ro_field {sw = r; hw = w;};
+    field wo_field {sw = w; hw = r;};
+    //--------------------------------------------------------------------------
+    // Overlapping registers
+    //--------------------------------------------------------------------------
+    // Simple overlap
+    reg {
+        ro_field f;
+    } r0_ro @ 0x0;
+    reg {
+        wo_field f;
+    } r0_wo @ 0x0;
+
+    // Offset overlap
+    reg {
+        ro_field f;
+    } r1_ro @ 0x10;
+    reg {
+        wo_field f;
+    } r1_wo @ 0x11;
+
+    // Wide + narrow multiple overlaps
+    reg {
+        regwidth = 32;
+        ro_field f;
+    } r2_ro @ 0x100;
+    reg {
+        regwidth = 8;
+        wo_field f;
+    } r2_wo_a @ 0x100,
+    r2_wo_b @ 0x101,
+    r2_wo_c @ 0x102,
+    r2_wo_d @ 0x103;
+
+    // Narrow + wide multiple overlaps
+    reg {
+        regwidth = 8;
+        ro_field f;
+    } r3_ro_a @ 0x200,
+    r3_ro_b @ 0x201,
+    r3_ro_c @ 0x202,
+    r3_ro_d @ 0x203;
+    reg {
+        regwidth = 32;
+        wo_field f;
+    } r3_wo @ 0x200;
+
+
+    reg {
+        ro_field f1;
+        wo_field f2;
+    } r4 @ 0x300;
+
+    //--------------------------------------------------------------------------
+    // Overlapping fields
+    //--------------------------------------------------------------------------
+
+    reg {
+        ro_field f_ro[7:0];
+        wo_field f_wo[7:0];
+    } simple_overlap;
+
+    reg {
+        ro_field f_ro[7:0];
+        wo_field f_wo[12:4];
+    } offset_overlap;
+
+    reg {
+        ro_field f_ro[31:0];
+        wo_field f_wo_a[7:0];
+        wo_field f_wo_b[15:8];
+        wo_field f_wo_c[23:16];
+        wo_field f_wo_d[31:24];
+    } wide_narrow_overlap;
+
+    reg {
+        ro_field f_ro_a[7:0];
+        ro_field f_ro_b[15:8];
+        ro_field f_ro_c[23:16];
+        ro_field f_ro_d[31:24];
+        wo_field f_wo[31:0];
+    } narrow_wide_overlap;
+};
diff --git a/test/test_overlaps.py b/test/test_overlaps.py
@@ -0,0 +1,152 @@
+from systemrdl.node import RegNode, FieldNode
+
+from unittest_utils import RDLSourceTestCase
+
+class TestOverlaps(RDLSourceTestCase):
+
+    def test_reg_overlaps(self):
+        root = self.compile(
+            ["rdl_src/overlaps.rdl"],
+            "top"
+        )
+        top = root.top
+
+        r0_ro: RegNode = top.get_child_by_name("r0_ro")
+        r0_wo: RegNode = top.get_child_by_name("r0_wo")
+        r1_ro: RegNode = top.get_child_by_name("r1_ro")
+        r1_wo: RegNode = top.get_child_by_name("r1_wo")
+        r2_ro: RegNode = top.get_child_by_name("r2_ro")
+        r2_wo_a: RegNode = top.get_child_by_name("r2_wo_a")
+        r2_wo_b: RegNode = top.get_child_by_name("r2_wo_b")
+        r2_wo_c: RegNode = top.get_child_by_name("r2_wo_c")
+        r2_wo_d: RegNode = top.get_child_by_name("r2_wo_d")
+        r3_ro_a: RegNode = top.get_child_by_name("r3_ro_a")
+        r3_ro_b: RegNode = top.get_child_by_name("r3_ro_b")
+        r3_ro_c: RegNode = top.get_child_by_name("r3_ro_c")
+        r3_ro_d: RegNode = top.get_child_by_name("r3_ro_d")
+        r3_wo: RegNode = top.get_child_by_name("r3_wo")
+        r4: RegNode = top.get_child_by_name("r4")
+
+        self.assertTrue(r0_ro.has_overlaps)
+        self.assertTrue(r0_wo.has_overlaps)
+        self.assertListEqual(r0_ro.overlapping_regs, [r0_wo])
+        self.assertListEqual(r0_wo.overlapping_regs, [r0_ro])
+
+        self.assertTrue(r1_ro.has_overlaps)
+        self.assertTrue(r1_wo.has_overlaps)
+        self.assertListEqual(r1_ro.overlapping_regs, [r1_wo])
+        self.assertListEqual(r1_wo.overlapping_regs, [r1_ro])
+
+        self.assertTrue(r2_ro.has_overlaps)
+        self.assertTrue(r2_wo_a.has_overlaps)
+        self.assertTrue(r2_wo_b.has_overlaps)
+        self.assertTrue(r2_wo_c.has_overlaps)
+        self.assertTrue(r2_wo_d.has_overlaps)
+        self.assertListEqual(r2_ro.overlapping_regs, [
+            r2_wo_a,
+            r2_wo_b,
+            r2_wo_c,
+            r2_wo_d,
+        ])
+        self.assertListEqual(r2_wo_a.overlapping_regs, [r2_ro])
+        self.assertListEqual(r2_wo_b.overlapping_regs, [r2_ro])
+        self.assertListEqual(r2_wo_c.overlapping_regs, [r2_ro])
+        self.assertListEqual(r2_wo_d.overlapping_regs, [r2_ro])
+
+        self.assertTrue(r3_ro_a.has_overlaps)
+        self.assertTrue(r3_ro_b.has_overlaps)
+        self.assertTrue(r3_ro_c.has_overlaps)
+        self.assertTrue(r3_ro_d.has_overlaps)
+        self.assertTrue(r3_wo.has_overlaps)
+        self.assertListEqual(r3_ro_a.overlapping_regs, [r3_wo])
+        self.assertListEqual(r3_ro_b.overlapping_regs, [r3_wo])
+        self.assertListEqual(r3_ro_c.overlapping_regs, [r3_wo])
+        self.assertListEqual(r3_ro_d.overlapping_regs, [r3_wo])
+        self.assertListEqual(r3_wo.overlapping_regs, [
+            r3_ro_a,
+            r3_ro_b,
+            r3_ro_c,
+            r3_ro_d,
+        ])
+
+        self.assertFalse(r4.has_overlaps)
+        self.assertListEqual(r4.overlapping_regs, [])
+
+
+    def test_field_overlaps(self):
+        root = self.compile(
+            ["rdl_src/overlaps.rdl"],
+            "top"
+        )
+        top = root.top
+
+        with self.subTest("simple"):
+            f_ro: FieldNode = top.find_by_path("simple_overlap.f_ro")
+            f_wo: FieldNode = top.find_by_path("simple_overlap.f_wo")
+            self.assertTrue(f_ro.has_overlaps)
+            self.assertTrue(f_wo.has_overlaps)
+            self.assertListEqual(f_ro.overlapping_fields, [f_wo])
+            self.assertListEqual(f_wo.overlapping_fields, [f_ro])
+
+        with self.subTest("offset"):
+            f_ro = top.find_by_path("offset_overlap.f_ro")
+            f_wo = top.find_by_path("offset_overlap.f_wo")
+            self.assertTrue(f_ro.has_overlaps)
+            self.assertTrue(f_wo.has_overlaps)
+            self.assertListEqual(f_ro.overlapping_fields, [f_wo])
+            self.assertListEqual(f_wo.overlapping_fields, [f_ro])
+
+        with self.subTest("wide_narrow"):
+            f_ro: FieldNode = top.find_by_path("wide_narrow_overlap.f_ro")
+            f_wo_a: FieldNode = top.find_by_path("wide_narrow_overlap.f_wo_a")
+            f_wo_b: FieldNode = top.find_by_path("wide_narrow_overlap.f_wo_b")
+            f_wo_c: FieldNode = top.find_by_path("wide_narrow_overlap.f_wo_c")
+            f_wo_d: FieldNode = top.find_by_path("wide_narrow_overlap.f_wo_d")
+
+            self.assertTrue(f_ro.has_overlaps)
+            self.assertTrue(f_wo_a.has_overlaps)
+            self.assertTrue(f_wo_b.has_overlaps)
+            self.assertTrue(f_wo_c.has_overlaps)
+            self.assertTrue(f_wo_d.has_overlaps)
+            self.assertListEqual(f_ro.overlapping_fields, [
+                f_wo_a,
+                f_wo_b,
+                f_wo_c,
+                f_wo_d,
+            ])
+            self.assertListEqual(f_wo_a.overlapping_fields, [f_ro])
+            self.assertListEqual(f_wo_b.overlapping_fields, [f_ro])
+            self.assertListEqual(f_wo_c.overlapping_fields, [f_ro])
+            self.assertListEqual(f_wo_d.overlapping_fields, [f_ro])
+
+        with self.subTest("narrow_wide"):
+            f_ro_a: FieldNode = top.find_by_path("narrow_wide_overlap.f_ro_a")
+            f_ro_b: FieldNode = top.find_by_path("narrow_wide_overlap.f_ro_b")
+            f_ro_c: FieldNode = top.find_by_path("narrow_wide_overlap.f_ro_c")
+            f_ro_d: FieldNode = top.find_by_path("narrow_wide_overlap.f_ro_d")
+            f_wo: FieldNode = top.find_by_path("narrow_wide_overlap.f_wo")
+
+            self.assertTrue(f_ro_a.has_overlaps)
+            self.assertTrue(f_ro_b.has_overlaps)
+            self.assertTrue(f_ro_c.has_overlaps)
+            self.assertTrue(f_ro_d.has_overlaps)
+            self.assertTrue(f_wo.has_overlaps)
+            self.assertListEqual(f_ro_a.overlapping_fields, [f_wo])
+            self.assertListEqual(f_ro_b.overlapping_fields, [f_wo])
+            self.assertListEqual(f_ro_c.overlapping_fields, [f_wo])
+            self.assertListEqual(f_ro_d.overlapping_fields, [f_wo])
+            self.assertListEqual(f_wo.overlapping_fields, [
+                f_ro_a,
+                f_ro_b,
+                f_ro_c,
+                f_ro_d,
+            ])
+
+        with self.subTest("no overlap"):
+            f1: FieldNode = top.find_by_path("r4.f1")
+            f2: FieldNode = top.find_by_path("r4.f2")
+
+            self.assertFalse(f1.has_overlaps)
+            self.assertFalse(f2.has_overlaps)
+            self.assertListEqual(f1.overlapping_fields, [])
+            self.assertListEqual(f2.overlapping_fields, [])
diff --git a/test/test_signals.py b/test/test_signals.py
@@ -1,6 +1,6 @@
 from unittest_utils import RDLSourceTestCase
 
-class TestParameters(RDLSourceTestCase):
+class TestSignals(RDLSourceTestCase):
 
     def test_signalwidth(self):
         root = self.compile(
