|
1 | 1 | import glob |
2 | 2 | import os |
3 | | -from typing import Union, List, Optional |
| 3 | +from typing import Union, List, Optional, Dict, Any |
4 | 4 | import sys |
5 | 5 |
|
6 | 6 | from typing_extensions import Literal, get_overloads, get_type_hints |
|
10 | 10 | from lib.type_hint_utils import value_is_compatible, hint_is |
11 | 11 | from systemrdl.node import AddressableNode, FieldNode, MemNode, Node, AddrmapNode, RegNode, RegfileNode, RootNode, SignalNode, VectorNode |
12 | 12 | from systemrdl import component as comp |
| 13 | +from systemrdl.source_ref import SourceRefBase |
13 | 14 | from unittest_utils import RDLSourceTestCase |
14 | 15 |
|
15 | 16 | from systemrdl.walker import RDLListener, RDLSimpleWalker |
@@ -114,19 +115,25 @@ def enter_Component(self, node: Node) -> None: |
114 | 115 | self.test_class.assert_attr_type_hint(node, "inst_name", str) |
115 | 116 | self.test_class.assert_attr_type_hint(node, "type_name", Optional[str]) |
116 | 117 | self.test_class.assert_attr_type_hint(node, "orig_type_name", Optional[str]) |
| 118 | + self.test_class.assert_attr_type_hint(node, "inst_src_ref", Optional[SourceRefBase]) |
| 119 | + self.test_class.assert_attr_type_hint(node, "def_src_ref", Optional[SourceRefBase]) |
| 120 | + self.test_class.assert_attr_type_hint(node, "property_src_ref", Dict[str, SourceRefBase]) |
| 121 | + self.test_class.assert_attr_type_hint(node, "parameters", Dict[str, Any]) |
117 | 122 | self.test_class.assert_attr_type_hint(node, "external", bool) |
| 123 | + self.test_class.assert_attr_type_hint(node, "cpuif_reset", Optional[SignalNode]) |
118 | 124 |
|
119 | 125 | def enter_AddressableComponent(self, node: AddressableNode) -> None: |
120 | 126 | self.test_class.assert_attr_type_hint(node, "raw_address_offset", int) |
121 | 127 | self.test_class.assert_attr_type_hint(node, "raw_absolute_address", int) |
122 | 128 | self.test_class.assert_attr_type_hint(node, "size", int) |
123 | 129 | self.test_class.assert_attr_type_hint(node, "total_size", int) |
124 | | - if node.is_array: |
| 130 | + if node.is_array is True: |
125 | 131 | self.test_class.assert_attr_type_hint(node, "array_dimensions", List[int]) |
126 | 132 | self.test_class.assert_attr_type_hint(node, "array_stride", int) |
127 | 133 | else: |
128 | 134 | self.test_class.assertIsNone(node.array_dimensions) |
129 | 135 | self.test_class.assertIsNone(node.array_stride) |
| 136 | + self.test_class.assert_attr_type_hint(node, "n_elements", int) |
130 | 137 |
|
131 | 138 |
|
132 | 139 | def enter_VectorComponent(self, node: VectorNode) -> None: |
@@ -159,6 +166,7 @@ def enter_Reg(self, node: RegNode) -> None: |
159 | 166 | self.test_class.assert_attr_type_hint(node, "parent", Union[AddrmapNode, RegfileNode, MemNode]) |
160 | 167 | self.test_class.assert_attr_type_hint(node, "inst", comp.Reg) |
161 | 168 | self.test_class.assert_attr_type_hint(node, "size", int) |
| 169 | + self.test_class.assert_attr_type_hint(node, "is_msb0_order", bool) |
162 | 170 | self.test_class.assert_attr_type_hint(node, "is_virtual", bool) |
163 | 171 | self.test_class.assert_attr_type_hint(node, "has_sw_writable", bool) |
164 | 172 | self.test_class.assert_attr_type_hint(node, "has_sw_readable", bool) |
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