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Add: Seeeduino Xiao Hardware SPI slave
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‎.travis.yml‎

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- export BOARD=Seeeduino:samd:seeed_wio_terminal
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- buildExampleSketch WioTerminal_Https_Stock_Demo;
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- echo "*************************************SeeeduinoXIAO_SPISlave*********************************************"
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- rm -rf $HOME/Arduino/libraries/*
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- rm -rf /tmp/arduino*
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- export BOARD=Seeeduino:samd:seeed_XIAO_m0
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- buildExampleSketch SeeeduinoXIAO_SPISlave;
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notifications:
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webhooks:
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urls:

‎examples/SeeeduinoXIAO_SPISlave/SeeeduinoXIAO_SPISlave.ino‎

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/*
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* Seeeduino XIAO Hardware SPI Slave
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*
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* Thanks goes out to:
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* jeremyherbert - https://github.com/jeremyherbert/playful-turtle-xiao
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* The atmel SAMD21 library
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* and everyone at https://forum.arduino.cc/index.php?topic=360026.0
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*
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* Notes:
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* - We are NOT using the default SPI pins per the Seeeduino documentation - we are reassigning these pins to SERCOM0.
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* - MOSI and MISO should be connected direct to the SPI master device - do not reverse/swap them.
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* - If you are only receiving/listening, then you can leave pin MISO pin 4 disconnected.
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* - You can use Serial for USB and Serial1 for UART TX/RX
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*
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* Wiring:
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* SPI_MOSI - Board Pin: 2 - Connect to MOSI on master
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* SPI_SCK - Board Pin: 3
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* SPI_MISO - Board Pin: 4 - Connect to MISO on master
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* SPI_CS - Board Pin: 5
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*/
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// DO NOT CHANGE PIN ASSIGMENTS UNLESS YOU KNOW WHAT YOU ARE DOING
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// ---- Seeeduino XIAO SPI ----
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// Board pin is the numbered pin on the Seeeduino XIAO board (connect wires to these pins)
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#define SPI_MOSI_B_PIN 2 // Board Pin
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#define SPI_SCK_B_PIN 3 // Board Pin
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#define SPI_MISO_B_PIN 4 // Board Pin
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#define SPI_CS_B_PIN 5 // Board Pin
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// Chip pin is the GPIO pin on the SAMD21 Microcontroller chip (internal only, you can ignore these)
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#define SPI_MOSI_PIN 10 // Chip Pin SERCOM PAD2
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#define SPI_SCK_PIN 11 // Chip Pin SERCOM PAD3
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#define SPI_MISO_PIN 8 // Chip Pin SERCOM PAD0
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#define SPI_CS_PIN 9 // Chip Pin SERCOM PAD1
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// Macros for the pin and port group
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#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
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#define GPIO_PORT(n) ((n) >> 5)
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#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
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#define GPIO_PIN_FUNCTION_OFF 0xffffffff
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// Port Critical Sections
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#if defined(ENABLE_PORT_CRITICAL_SECTIONS)
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#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define PORT_CRITICAL_SECTION_ENTER()
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#define PORT_CRITICAL_SECTION_LEAVE()
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#endif
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// Variables
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typedef uint8_t hri_port_pmux_reg_t;
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void setup() {
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// Set all pins are input so we don't disrupt comminication on boot
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pinMode(SPI_MOSI_B_PIN, INPUT);
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pinMode(SPI_SCK_B_PIN, INPUT);
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pinMode(SPI_MISO_B_PIN, INPUT);
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pinMode(SPI_CS_B_PIN, INPUT);
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// init Serial USB
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Serial.begin(115200);//for debugging
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//wait for serial to init
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while (!Serial);
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// Seeduino XIAO - Enable SPI as Slave
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Seeeduino_spiSlave_init();
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#ifdef ENABLE_PORT_CRITICAL_SECTIONS
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Serial.println("ENABLE_PORT_CRITICAL_SECTIONS is defined from the start")
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#endif
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}
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void loop() {
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}
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void Seeeduino_spiSlave_init()
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{
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// assign our board pins to SERCOM0
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gpio_set_pin_function(SPI_MOSI_PIN, PINMUX_PA10C_SERCOM0_PAD2);
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gpio_set_pin_function(SPI_SCK_PIN, PINMUX_PA11C_SERCOM0_PAD3);
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gpio_set_pin_function(SPI_MISO_PIN, PINMUX_PA08C_SERCOM0_PAD0);
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gpio_set_pin_function(SPI_CS_PIN, PINMUX_PA09C_SERCOM0_PAD1);
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//Disable SPI 0
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SERCOM0->SPI.CTRLA.bit.ENABLE = 0;
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while (SERCOM0->SPI.SYNCBUSY.bit.ENABLE);
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//Reset SPI 0
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SERCOM0->SPI.CTRLA.bit.SWRST = 1;
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while (SERCOM0->SPI.CTRLA.bit.SWRST || SERCOM0->SPI.SYNCBUSY.bit.SWRST);
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//Setting up NVIC
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NVIC_EnableIRQ(SERCOM0_IRQn);
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NVIC_SetPriority(SERCOM0_IRQn, 2);
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//Setting Generic Clock Controller!!!!
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(GCM_SERCOM0_CORE) | //Generic Clock 0
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GCLK_CLKCTRL_GEN_GCLK0 | // Generic Clock Generator 0 is the source
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GCLK_CLKCTRL_CLKEN; // Enable Generic Clock Generator
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY); //Wait for synchronisation
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//Set up SPI Control A Register
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SERCOM0->SPI.CTRLA.bit.DORD = 0; //MSB first
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SERCOM0->SPI.CTRLA.bit.CPOL = 0; //SCK is low when idle, leading edge is rising edge
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SERCOM0->SPI.CTRLA.bit.CPHA = 0; //data sampled on leading sck edge and changed on a trailing sck edge
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SERCOM0->SPI.CTRLA.bit.FORM = 0x0; //Frame format = SPI
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SERCOM0->SPI.CTRLA.bit.DIPO = 2; //DATA PAD0 MOSI is used as input (slave mode)
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SERCOM0->SPI.CTRLA.bit.DOPO = 1; //DATA PAD3 MISO is used as output
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//SERCOM0->SPI.CTRLA.bit.DIPO = 0; //DATA PAD0 MOSI is used as input (slave mode)
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//SERCOM0->SPI.CTRLA.bit.DOPO = 0x2; //DATA PAD3 MISO is used as output
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SERCOM0->SPI.CTRLA.bit.MODE = 0x2; //SPI in Slave mode
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SERCOM0->SPI.CTRLA.bit.IBON = 0x1; //Buffer Overflow notification
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SERCOM0->SPI.CTRLA.bit.RUNSTDBY = 1; //wake on receiver complete
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//Set up SPI control B register
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//SERCOM0->SPI.CTRLB.bit.RXEN = 0x1; //Enable Receiver
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SERCOM0->SPI.CTRLB.bit.SSDE = 0x1; //Slave Selecte Detection Enabled
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SERCOM0->SPI.CTRLB.bit.CHSIZE = 0; //character size 8 Bit
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//SERCOM0->SPI.CTRLB.bit.PLOADEN = 0x1; //Enable Preload Data Register
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//while (SERCOM0->SPI.SYNCBUSY.bit.CTRLB);
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//Set up SPI interrupts
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SERCOM0->SPI.INTENSET.bit.SSL = 0x1; //Enable Slave Select low interrupt
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SERCOM0->SPI.INTENSET.bit.RXC = 0x1; //Receive complete interrupt
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SERCOM0->SPI.INTENSET.bit.TXC = 0x1; //Receive complete interrupt
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SERCOM0->SPI.INTENSET.bit.ERROR = 0x1; //Receive complete interrupt
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SERCOM0->SPI.INTENSET.bit.DRE = 0x1; //Data Register Empty interrupt
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//init SPI CLK
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//SERCOM0->SPI.BAUD.reg = SERCOM_FREQ_REF / (2*4000000u)-1;
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//Enable SPI
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SERCOM0->SPI.CTRLA.bit.ENABLE = 1;
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while (SERCOM0->SPI.SYNCBUSY.bit.ENABLE);
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SERCOM0->SPI.CTRLB.bit.RXEN = 0x1; //Enable Receiver, this is done here due to errate issue
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while (SERCOM0->SPI.SYNCBUSY.bit.CTRLB); //wait until receiver is enabled
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}
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// Seeduino SPI interrupt routine
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void SERCOM0_Handler()
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{
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noInterrupts();
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uint8_t data = 0;
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uint8_t interrupts = SERCOM0->SPI.INTFLAG.reg; //Read SPI interrupt register
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if (interrupts & (1 << 3))
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{
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SERCOM0->SPI.INTFLAG.bit.SSL = 1; //clear slave select interrupt
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}
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// This is where data is received, and is written to a buffer, which is used in the main loop
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if (interrupts & (1 << 2))
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{
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data = SERCOM0->SPI.DATA.reg; //Read data register
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SERCOM0->SPI.INTFLAG.bit.RXC = 1; //clear receive complete interrupt
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// Put the data somewhere, like a buffer - or print it for testing
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Serial.println(data, DEC); // print received data as a number
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}
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// This is where data is transmitted
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if (interrupts & (1 << 1))
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{
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SERCOM0->SPI.INTFLAG.bit.TXC = 1; //clear transmit complete interrupt
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}
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// Data Register Empty Interrupt
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if (interrupts & (1 << 0))
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{
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SERCOM0->SPI.DATA.reg = 0xAA;
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}
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interrupts();
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}
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static inline void gpio_set_pin_function(const uint32_t gpio, const uint32_t function)
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{
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uint8_t port = GPIO_PORT(gpio);
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uint8_t pin = GPIO_PIN(gpio);
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if (function == GPIO_PIN_FUNCTION_OFF) {
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hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false);
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} else {
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hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true);
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if (pin & 1) {
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// Odd numbered pin
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hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff);
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} else {
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// Even numbered pin
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hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff);
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}
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}
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}
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static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index,
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bool value)
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{
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uint8_t tmp;
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PORT_CRITICAL_SECTION_ENTER();
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tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg;
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tmp &= ~PORT_PINCFG_PMUXEN;
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tmp |= value << PORT_PINCFG_PMUXEN_Pos;
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((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp;
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PORT_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
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hri_port_pmux_reg_t data)
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{
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uint8_t tmp;
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PORT_CRITICAL_SECTION_ENTER();
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tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
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tmp &= ~PORT_PMUX_PMUXO_Msk;
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tmp |= PORT_PMUX_PMUXO(data);
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((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
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PORT_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index,
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hri_port_pmux_reg_t data)
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{
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uint8_t tmp;
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PORT_CRITICAL_SECTION_ENTER();
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tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg;
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tmp &= ~PORT_PMUX_PMUXE_Msk;
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tmp |= PORT_PMUX_PMUXE(data);
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((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp;
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PORT_CRITICAL_SECTION_LEAVE();
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}

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