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ChoiCube84ChoiCube84
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Merge pull request #208 from RISC-KC/feat/csr_file
[Feat] Revise CSR File mcycle minstret logic with permission level and its testbench
2 parents b0ca0b8 + 0f88394 commit 80f241d

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3 files changed

+466
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‎modules/CSR_File.v‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ module CSRFile #(
1010
input [11:0] csr_read_address, // address to read
1111
input [11:0] csr_write_address, // address to write
1212
input [XLEN-1:0] csr_write_data, // data to write
13+
input instruction_retired,
1314

1415
output reg [XLEN-1:0] csr_read_out, // data from CSR Unit
1516
output reg csr_ready // signal to stall the process while accessing the CSR until it outputs the desired value.
@@ -106,6 +107,12 @@ module CSRFile #(
106107
csr_read_out <= {XLEN{1'b0}};
107108
csr_write_enable_buffer <= 1'b0;
108109
end else begin
110+
mcycle <= mcycle + 1;
111+
112+
if (instruction_retired) begin
113+
minstret <= minstret + 1;
114+
end
115+
109116
if (csr_access && !csr_processing) begin
110117
csr_processing <= 1'b1;
111118
csr_read_out <= csr_read_data;
@@ -124,10 +131,6 @@ module CSRFile #(
124131
12'h305: mtvec <= csr_write_data;
125132
12'h341: mepc <= csr_write_data;
126133
12'h342: mcause <= csr_write_data;
127-
12'hB00: mcycle[31:0] <= csr_write_data;
128-
12'hB80: mcycle[63:32] <= csr_write_data;
129-
12'hB02: minstret[31:0] <= csr_write_data;
130-
12'hB82: minstret[63:32] <= csr_write_data;
131134
default: ;
132135
endcase
133136
end

‎testbenches/CSR_File_tb.v‎

Lines changed: 55 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ module CSRFile_tb;
88
reg [11:0] csr_read_address;
99
reg [11:0] csr_write_address;
1010
reg [31:0] csr_write_data;
11+
reg instruction_retired;
1112

1213
wire [31:0] csr_read_out;
1314
wire csr_ready;
@@ -20,6 +21,7 @@ module CSRFile_tb;
2021
.csr_read_address(csr_read_address),
2122
.csr_write_address(csr_write_address),
2223
.csr_write_data(csr_write_data),
24+
.instruction_retired(instruction_retired),
2325

2426
.csr_read_out(csr_read_out),
2527
.csr_ready(csr_ready)
@@ -39,6 +41,7 @@ module CSRFile_tb;
3941
csr_read_address = 12'h000;
4042
csr_write_address = 12'h000;
4143
csr_write_data = 32'h0;
44+
instruction_retired = 0;
4245
#10;
4346
reset = 0;
4447
#10;
@@ -48,6 +51,8 @@ module CSRFile_tb;
4851
$display("mvendorid = %h (expected 52564B43)", csr_read_out);
4952

5053
csr_read_address = 12'hF12; #10;
54+
instruction_retired = 1'b1; #10;
55+
instruction_retired = 1'b0;
5156
$display("marchid = %h (expected 34365335)", csr_read_out);
5257

5358
csr_read_address = 12'hF13; #10;
@@ -134,22 +139,22 @@ module CSRFile_tb;
134139

135140
$display("Write ignored : mvendorid = %h (expected 52564B43)", csr_read_out);
136141

137-
// Test 7: mcycle/minstret reset value check
142+
// Test 7: mcycle/minstret auto-increment check (read-only counters)
138143
csr_read_address = 12'hB00; #10;
139-
$display("mcycle (lower 32-bit, reset) = %h (expected 00000000)", csr_read_out);
144+
$display("mcycle (lower 32-bit) = %h (auto-incremented, not 0)", csr_read_out);
140145

141146
csr_read_address = 12'hB80; #10;
142-
$display("mcycleh (upper 32-bit, reset) = %h (expected 00000000)", csr_read_out);
147+
$display("mcycleh (upper 32-bit) = %h (should be 0, no overflow yet)", csr_read_out);
143148

144149
csr_read_address = 12'hB02; #10;
145-
$display("minstret (lower 32-bit, reset) = %h (expected 00000000)", csr_read_out);
150+
$display("minstret (lower 32-bit) = %h (should be 1, one instruction retired in Test 1)", csr_read_out);
146151

147152
csr_read_address = 12'hB82; #10;
148-
$display("minstreth (upper 32-bit, reset) = %h (expected 00000000)", csr_read_out);
153+
$display("minstreth (upper 32-bit) = %h (should be 0, no overflow yet)", csr_read_out);
149154

150-
// Test 8: csrrw; mcycle lower 32-bit
155+
// Test 8: Read-only test for mcycle - write should be ignored
151156
csr_read_address = 12'hB00; #10;
152-
$display("mcycle (before write) = %h (expected 00000000)", csr_read_out);
157+
$display("mcycle (before write attempt) = %h", csr_read_out);
153158

154159
csr_write_address = 12'hB00;
155160
csr_write_data = 32'h12345678;
@@ -160,11 +165,11 @@ module CSRFile_tb;
160165
#10;
161166

162167
csr_read_address = 12'hB00; #10;
163-
$display("mcycle (after write) = %h (expected 12345678)", csr_read_out);
168+
$display("mcycle (after write attempt) = %h (write should be ignored, auto-incremented)", csr_read_out);
164169

165-
// Test 9: csrrw; mcycleh upper 32-bit
170+
// Test 9: Read-only test for mcycleh - write should be ignored
166171
csr_read_address = 12'hB80; #10;
167-
$display("mcycleh (before write) = %h (expected 00000000)", csr_read_out);
172+
$display("mcycleh (before write attempt) = %h", csr_read_out);
168173

169174
csr_write_address = 12'hB80;
170175
csr_write_data = 32'hABCDEF00;
@@ -175,17 +180,11 @@ module CSRFile_tb;
175180
#10;
176181

177182
csr_read_address = 12'hB80; #10;
178-
$display("mcycleh (after write) = %h (expected ABCDEF00)", csr_read_out);
183+
$display("mcycleh (after write attempt) = %h (write should be ignored, should remain 0)", csr_read_out);
179184

180-
csr_read_address = 12'hB00; #10;
181-
$display("mcycle (should remain) = %h (expected 12345678)", csr_read_out);
182-
183-
$display("Full 64-bit mcycle = %h_%h (expected ABCDEF00_12345678)",
184-
csr_file.mcycle[63:32], csr_file.mcycle[31:0]);
185-
186-
// Test 10: csrrw; minstret lower 32-bit
185+
// Test 10: Read-only test for minstret - write should be ignored
187186
csr_read_address = 12'hB02; #10;
188-
$display("minstret (before write) = %h (expected 00000000)", csr_read_out);
187+
$display("minstret (before write attempt) = %h", csr_read_out);
189188

190189
csr_write_address = 12'hB02;
191190
csr_write_data = 32'hDEADBEEF;
@@ -196,11 +195,11 @@ module CSRFile_tb;
196195
#10;
197196

198197
csr_read_address = 12'hB02; #10;
199-
$display("minstret (after write) = %h (expected DEADBEEF)", csr_read_out);
198+
$display("minstret (after write attempt) = %h (write should be ignored, should remain 1)", csr_read_out);
200199

201-
// Test 11: csrrw; minstreth upper 32-bit
200+
// Test 11: Read-only test for minstreth - write should be ignored
202201
csr_read_address = 12'hB82; #10;
203-
$display("minstreth (before write) = %h (expected 00000000)", csr_read_out);
202+
$display("minstreth (before write attempt) = %h", csr_read_out);
204203

205204
csr_write_address = 12'hB82;
206205
csr_write_data = 32'hCAFEBABE;
@@ -211,15 +210,42 @@ module CSRFile_tb;
211210
#10;
212211

213212
csr_read_address = 12'hB82; #10;
214-
$display("minstreth (after write) = %h (expected CAFEBABE)", csr_read_out);
213+
$display("minstreth (after write attempt) = %h (write should be ignored, should remain 0)", csr_read_out);
215214

216-
csr_read_address = 12'hB02; #10;
217-
$display("minstret (should remain) = %h (expected DEADBEEF)", csr_read_out);
215+
// Test 12: mcycle auto-increment verification
216+
$display("\n=== Auto-increment verification ===");
217+
csr_read_address = 12'hB00;
218+
#10;
219+
$display("mcycle at T0 = %h", csr_read_out);
220+
#20; // Wait 2 cycles
221+
csr_read_address = 12'hB00;
222+
#10;
223+
$display("mcycle at T0+2 = %h (should be +2 from previous)", csr_read_out);
224+
225+
// Test 13: minstret increment with instruction_retired
226+
$display("\n=== instruction_retired test ===");
227+
csr_read_address = 12'hB02;
228+
#10;
229+
$display("minstret before retired = %h", csr_read_out);
230+
231+
instruction_retired = 1;
232+
#10;
233+
instruction_retired = 0;
234+
csr_read_address = 12'hB02;
235+
#10;
236+
$display("minstret after 1 retired = %h (should be +1)", csr_read_out);
218237

219-
$display("Full 64-bit minstret = %h_%h (expected CAFEBABE_DEADBEEF)",
220-
csr_file.minstret[63:32], csr_file.minstret[31:0]);
238+
instruction_retired = 1;
239+
#10;
240+
instruction_retired = 1;
241+
#10;
242+
instruction_retired = 0;
243+
csr_read_address = 12'hB02;
244+
#10;
245+
$display("minstret after 2 more retired = %h (should be +2)", csr_read_out);
221246

222-
// Test 12: Full 64-bit value integrity check
247+
// Final values
248+
$display("\n=== Final Counter Values ===");
223249
csr_read_address = 12'hB00; #10;
224250
$display("Final mcycle[31:0] = %h", csr_read_out);
225251

@@ -234,7 +260,7 @@ module CSRFile_tb;
234260
$display("Final minstret[63:32] = %h", csr_read_out);
235261
$display("Final Full minstret = 0x%h_%h", csr_file.minstret[63:32], csr_file.minstret[31:0]);
236262

237-
$display("\n==================== Register File Test END ====================");
263+
$display("\n==================== CSR File Test END ====================");
238264
$stop;
239265
end
240266

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