Datapath Simulator

Datapath Simulator

The datapath simulator is incorporated into MARIE.js, and can be accessed via the menu: View -> Datapath.

The purpose of this visualisation is to give an understanding of how instructions and micro-instructions relate to sequence of physical signals.

Register bank

The MARIE simulator register bank is a set of 7 registers used for different purposes. For example, the PC register holds the memory address that points to the next instruction.

Here is a list of the registers used in the MARIE simulator.

Name	Opcode	Abbreviation	# of bits stored
Memory Address Register	001	MAR	12
Program Counter	010	PC	12
Memory Buffer Register	011	MBR	16
Accumulator	100	AC	16
Input	101	IN	16
Output	110	OUT	16
Instruction Register	111	IR	16

Memory

The memory stores data in a sequence of locations. At this point of time, nothing much is shown in the memory, apart from whether data is being read from or written to memory.

It is important to know that the data in each memory cell has no meaning in itself. For example, a memory cell may represent as data 0000 (which is very common as usually most of memory cells are empty), but can also be seen as a JnS instruction with memory address 000, as the highest hexadecimal value is the same as the opcode for the JnS instruction.

Read control bus

The read control bus tells which register (or memory) to output data into the data bus.

Abbreviation	Opcode	Activate Wires
M[MAR]	000*	Mr
MAR	001	P0
PC	010	P1
MBR	011	P1 P0
AC	100	P2
IN	101	P2 P0
OUT	110	P2 P1
IR	111	P2 P1 P0

* While the memory opcode is 000, it technically means that we do not want to access any register. This is the reason why we have a separate memory read wire so that we can tell the memory exactly when we want to fetch the contents of one memory cell.

Write control bus

The write control bus tells which register (or memory) to read from the data bus and override its value.

Abbreviation	Opcode	Activate Wires
M[MAR]	000*	Mw
MAR	001	P3
PC	010	P4
MBR	011	P4 P3
AC	100	P5
IN	101	P5 P3
OUT	110	P5 P4
IR	111	P5 P4 P3

* Like what is said previously in the read control bus section, this opcode just means do not write to any register. A separate memory write wire is activated instead when we need to write to memory.

ALU opcode signals

There are three wires to tell the ALU what kind of operation it needs to perform. Here are the following operations with their opcodes.

Operation	Opcode	Active Wires	RTL
Addition	001	A0	AC ← AC + MBR
Subtraction	010	A1	AC ← AC - MBR
Clear	011	A1 A0	AC ← 0
Increment PC if AC is negative	100	A2	AC < 0? If so then PC ← PC + 1
Increment PC if AC is zero	101	A2 A0	AC = 0? If so then PC ← PC + 1
Increment PC if AC is positive	110	A2 A1	AC > 0? If so then PC ← PC + 1
Increment PC	111	A2 A1 A0	PC ← PC + 1

Data bus

The data bus is 16 bits long, and is used for transferring data (which may hold memory addresses) between registers and/or the memory. It is connected to all registers as well as the memory.

Address bus

The address bus is 12-bits long, and is connected to both the MAR register and the memory.

Decode bus

The "decode bus" is 4-bits long, and is connected to both the IR register and the control unit. Only the highest 4 bits of the IR register is connected to the decode bus, which is used as input for decoding which instruction is needed to be executed.

The control unit, and putting it all together

The control unit handles both the register bank, the memory, and the ALU. It does this by generating a sequence of signals, depending on what instruction it has decoded. All instructions begin with the fetch cycle, which the control unit fetches the next instruction from memory, and increments the program counter. Once the instruction is decoded, it executes the instruction by performing the corresponding sequence of RTL operations. Each RTL operation has its own set of signals that needs to be generated.

The active 'LED' in the time sequence signal labelled Tn where n is an unsigned integer, shows how many RTL operations have been performed before the current one within the current instruction. These sequential signals are reset once the control unit has finished executing the current instruction and is ready to execute the next instruction.

The first three (T0, T1, T2) time sequence signals are dedicated to the fetch part of the fetch-decode-execute cycle. The rest of the time sequence depends on what instruction the control unit has decoded from the IR.