Upload verilog code files

Author: Bharadwaj-R

alu.v

@@ -0,0 +1,57 @@
+module alu(out, a, b, sel);
+
+output reg [3:0] out;
+input [3:0] a, b, sel;
+
+always @(a or b or sel) begin
+case (sel)
+4'b0000: out = a+b;
+4'b0001: out = a-b;
+4'b0010: out = a*b;
+4'b0011: out = a/b;
+4'b0100: out = a<<b;
+4'b0101: out = a>>b;
+4'b0110: out = {a[2:0], a[3]};
+4'b0111: out = {a[0], a[3:1]};
+4'b1000: out = a&b;
+4'b1001: out = a|b;
+4'b1010: out = a^b;
+4'b1011: out = ~(a|b);
+4'b1100: out = ~(a&b);
+4'b1101: out = ~(a^b);
+4'b1110: out = a>b?1:0;
+4'b1111: out = a==b?1:0;
+endcase
+end
+
+endmodule
+
+
+/* 
+module testbench;
+
+wire [3:0] out;
+reg [3:0] a, b, sel;
+
+alu chip1(out, a, b, sel);
+
+initial begin a = 4'b1010; b = 4'b0001;
+sel = 4'b0000; //out = a+b;
+#100 sel = 4'b0001; //out = a-b;
+#100 sel = 4'b0010; //out = a*b;
+#100 sel = 4'b0011; //out = a/b;
+#100 sel = 4'b0100; //out = a<<b;
+#100 sel = 4'b0101; //out = a>>b;
+#100 sel = 4'b0110; //rotated left
+#100 sel = 4'b0111; //rotated right
+#100 sel = 4'b1000; //out = a&b;
+#100 sel = 4'b1001; //out = a|b;
+#100 sel = 4'b1010; //out = a^b;
+#100 sel = 4'b1011; //out = ~(a|b);
+#100 sel = 4'b1100; //out = ~(a&b);
+#100 sel = 4'b1101; //out = ~(a^b);
+#100 sel = 4'b1110; //out = a>b?1:0;
+#100 sel = 4'b1111; //out = a==b?1:0;
+end
+endmodule
+*/

aoi.v

@@ -0,0 +1,25 @@
+module Aoi(a1,a2,b1,b2,o);
+input a1,a2,b1,b2;
+output  reg o;
+always@(a1 or a2 or b1 or b2) begin
+case({a1,a2,b1,b2})
+4'b0000: o=1;
+4'b0001: o=1;
+4'b0010: o=1;
+4'b0011: o=0;
+4'b0100: o=1;
+4'b0101: o=1;
+4'b0110: o=1;
+4'b0111: o=0;
+4'b1000: o=1;
+4'b1001: o=1;
+4'b1010: o=1;
+4'b1011: o=0;
+4'b1100: o=0;
+4'b1101: o=0;
+4'b1110: o=0;
+4'b1111: o=0;
+endcase
+end 
+endmodule
+

aoi_4.v

@@ -0,0 +1,8 @@
+module aoi_4(a,b,c,d,Y);
+input a,b,c,d;
+output Y;
+
+assign Y=~c&~d&(a~^b)+~c&d&(a^b)+c&~d&(a&b)+c&d&~(a&b);
+
+endmodule
+

aoi_4tb.v

@@ -0,0 +1,22 @@
+module test4;
+reg a,b,c,d;
+wire Y;
+aoi_4 tb(a,b,c,d,Y);
+initial begin 
+{a,b,c,d}=4'b0001;
+#100 {a,b,c,d}=4'b0010;
+#100{a,b,c,d}=4'b0100; 
+#100 {a,b,c,d}=4'b1000;
+#100{a,b,c,d}=4'b0011;
+#100{a,b,c,d}=4'b0101;
+#100{a,b,c,d}=4'b1001;
+#100{a,b,c,d}=4'b0110;
+#100{a,b,c,d}=4'b0111;
+#100{a,b,c,d}=4'b1011;
+#100{a,b,c,d}=4'b1100;
+#100{a,b,c,d}=4'b1001;
+#100{a,b,c,d}=4'b1010;
+#100{a,b,c,d}=4'b1110;
+#100{a,b,c,d}=4'b1111;
+end
+endmodule

aoitb.v

@@ -0,0 +1,24 @@
+module aoitb;
+reg a1,a2,b1,b2;
+wire o;
+Aoi go(a1,a2,b1,b2,o);
+initial begin
+{a1,a2,b1,b2} =4'b0000;
+#100 {a1,a2,b1,b2} =4'b0001;
+#100 {a1,a2,b1,b2} =4'b0010;
+#100 {a1,a2,b1,b2} =4'b0011;
+#100 {a1,a2,b1,b2} =4'b0100;
+#100 {a1,a2,b1,b2} =4'b0101;
+#100 {a1,a2,b1,b2} =4'b0110;
+#100 {a1,a2,b1,b2} =4'b0111;
+#100 {a1,a2,b1,b2} =4'b1000;
+#100 {a1,a2,b1,b2} =4'b1001;
+#100 {a1,a2,b1,b2} =4'b1010;
+#100 {a1,a2,b1,b2} =4'b1011;
+#100 {a1,a2,b1,b2} =4'b1100;
+#100 {a1,a2,b1,b2} =4'b1101;
+#100 {a1,a2,b1,b2} =4'b1110;
+#100 {a1,a2,b1,b2} =4'b1111;
+end
+endmodule
+ 

asynchronous_counter_4bit.v

@@ -0,0 +1,51 @@
+module asynchronous_counter_4bit(out, clk, reset, sel);
+
+input clk, reset, sel;
+output reg [3:0] out;
+
+initial out = 4'b0000;
+
+always @(posedge clk) begin
+
+if (sel == 0) begin
+if (out <= 15) begin
+out = out + 1;
+end
+end
+
+if(sel == 1) begin
+if (out >= 0) begin
+out = out - 1;
+end
+end
+
+if (reset == 1) out = 4'b0000;
+
+end
+
+endmodule
+
+
+/* Testbench
+module testbench;
+
+reg clk, reset, sel;
+wire [3:0]out;
+
+asynchronous_counter_4bit counter1(out, clk, reset, sel);
+
+initial begin
+clk = 0;
+forever #10 clk = ~clk;
+end
+
+initial begin
+reset = 0; sel = 0;
+#320
+reset = 0; sel = 1;
+#320
+reset = 1;
+end
+
+endmodule
+*/

asynchronous_dualport_RAM.v

@@ -0,0 +1,56 @@
+module async_dual_port_ram(
+input [7:0] data_a,data_b,
+input [5:0] addr_a,addr_b,
+input we_a, we_b,
+output reg [7:0] q_a,q_b
+);
+    reg [7:0] ram[63:0]; //64 * 8 bit
+    
+    always @ (data_a or addr_a or we_a)
+    begin
+        if(we_a)
+        begin
+            ram[addr_a]<=data_a; //write
+        end
+        else
+        begin
+            q_a<=ram[addr_a]; //read
+        end
+    end
+    
+    always @ (data_b or addr_b or we_b)
+    begin
+        if(we_b)
+        begin
+            ram[addr_b]<=data_b; //write
+        end
+        else
+        begin
+            q_b<=ram[addr_b]; //read
+        end
+    end
+endmodule
+
+
+/*
+module testbench;
+
+reg [7:0] data_a,data_b;
+reg [5:0] addr_a,addr_b;
+reg we_a, we_b;
+wire [7:0] q_a,q_b;
+
+async_dual_port_ram ram(data_a, data_b, addr_a, addr_b, we_a, we_b, q_a, q_b);
+
+initial begin
+we_a = 1; addr_a = 6'b00000; data_a = 8'b10101010;
+#100 we_a = 0; addr_a = 6'b00000; data_a = 7'd0;
+
+#100 we_b = 1; addr_b = 6'b00000; data_b = 8'b01010101; we_a = 1'bx; data_a = 8'bx; addr_a = 6'bx;
+#100 we_b = 0; addr_b = 6'b00000; data_b = 7'd0;
+
+#100 $finish;
+end
+
+endmodule
+*/

asynchronous_singleport_RAM.v

@@ -0,0 +1,39 @@
+module async_single_port_RAM (
+    input [7:0] data,
+    input [5:0] addr,
+    input we,
+    output [7:0] q
+    );
+    
+    reg [7:0] ram [63:0];
+    reg [5:0] addr_reg;
+    
+    always@(data or addr or we)
+    begin
+        if(we)
+            ram[addr]<=data;
+        else
+            addr_reg <=addr;
+    end
+    
+    assign q=ram[addr_reg];
+    
+endmodule
+
+/*
+module testbench;
+
+reg [7:0] data;
+reg [5:0] addr;
+reg we;
+wire [7:0] q;
+
+async_single_port_RAM ram(data, addr, we, q);
+
+initial begin
+we = 1; addr = 6'b00000; data = 8'b10101010;
+#100 we = 0; addr = 6'b00000; data = 7'd0;
+end
+endmodule
+*/
+

carry_lookahead_adder_4bit.v

@@ -0,0 +1,52 @@
+module carry_lookahead_adder_4bit(s, cout, x, y);
+
+input [3:0] x, y;
+output [3:0]s;
+output cout;
+
+wire [3:0] p, g, c;
+
+assign p[0] = x[0]^y[0];
+assign g[0] = x[0]&y[0];
+assign c[0] = 0;
+
+assign p[1] = x[1]^y[1];
+assign g[1] = x[1]&y[1];
+assign c[1] = g[0] | p[0]&c[0];
+
+assign p[2] = x[2]^y[2];
+assign g[2] = x[2]&y[2];
+assign c[2] = g[1] | p[1]&c[1];
+
+assign p[3] = x[3]^y[3];
+assign g[3] = x[3]&y[3];
+assign c[3] = g[2] | p[2]&c[2];
+
+assign s[0] = p[0]^c[0];
+assign s[1] = p[1]^c[1];
+assign s[2] = p[2]^c[2];
+assign s[3] = p[3]^c[3];
+
+assign cout = g[3] | p[3]&c[3];
+
+endmodule
+
+/*
+
+module testbench;
+
+reg [3:0] x, y;
+wire [3:0]s; 
+wire cout;
+
+carry_lookahead_adder_4bit cla1(s, cout, x, y);
+
+initial begin
+
+x = 4'b1010;
+y = 4'b1101;
+
+end
+endmodule
+*/
+

clock_divider.v

@@ -0,0 +1,43 @@
+module clock_divider(clkout, clkin);
+
+output reg clkout;
+input clkin;
+
+initial clkout = 0;
+integer n; initial n = 100000000; // n * 10nano = time in seconds in FPGA for 100MHz clk.
+integer counter; initial counter = 0;
+
+always @(posedge clkin) begin
+
+if (counter == n) begin
+clkout = ~clkout;
+counter = 1'b0;
+end
+
+else if (counter <= n) begin
+counter = counter + 1;
+end
+
+end
+
+endmodule
+
+/*
+module testbench;
+reg clk, n;
+wire out;
+
+clock_divider clkdvd(out, clk, 100);
+
+initial begin
+clk = 1'b0;
+forever #100 clk = ~clk;
+end
+
+initial begin
+n = 2;
+end
+
+endmodule
+
+*/