Running Ordt

Download Ordt.jar from the release area or create a runnable jar from source.

Running ordt requires Java version 1.7 or higher.

Command Syntax

Commands below assume the alias ordt is created for java -jar Ordt.jar

Usage:

 Open Register Design Tool (version 170513.01) usage: ordt [options] <input_rdl_or_jspec_file>
 Options:
    -parms <input_parms_filename>
        <input_parms_filename> will be used to set ordt control parameters. The -parms
        option may be specified multiple times to include multiple parameter files.
    -cppmod <dirname>
        <dirname> will be created containing C++ model output files
    -cppdrvmod <dirname>
        <dirname> will be created containing C++ driver model output files
    -jspec <filename>
        <filename> will be created containing jspec output
    -overlay <tag> <input_filename>
        <input_filename> will be processed as an overlay input with specified tag
    -reglist <filename>
        <filename> will be created containing a text listing of accessible registers
    -rdl <filename>
        <filename> will be created containing rdl output
    -systemverilog <output_name>
        if <output name> ends with '/', <output_name> will be a directory where multiple 
        systemverilog output files will be written.  Otherwise <output_name> will be a
        file containing systemverilog output for all generated modules.
    -svchildinfo <filename>
        <filename> will be created containing child decoder address information
    -uvmregs <filename>
        <filename> will be created containing UVM register classes
    -uvmregspkg <filename>
        <filename> will be created containing package of ordt extended UVM classes
    -xml <filename>
        <filename> will be created containing xml output

Examples

Create register rtl and uvm model from rdl input:

ordt -systemverilog rtlout.sv –uvmregs uvmout.sv –uvmregspkg uvmpkg.sv simple.rdl

Create register rtl from rdl input using a parameter file: (see here for more info on ordt control parameters)

ordt -systemverilog rtlout.sv –parms ordt.parms simple.rdl

Convert jspec to rdl:

ordt -rdl rdlout.rdl simple.js

Create text register list and xml document from rdl input:

ordt -reglist reglist.txt –xml reginfo.xml simple.rdl

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Input file pre-processors

Ordt does not natively support pre-processing of rdl or js input files. In more complex design flows, it is very useful to include input files hierarchically, define macros, and selectively control input processing using variables. A variety of 3rd party text preprocessing packages are available to support some/all of these functions - a few are listed below for reference, but these have not been verified to interoperate with ordt:

• System-RDL-preprocess (SystemRDL 1.0 preprocessor support) - https://github.com/gxwcxl2010/System-RDL-preprocess *
• vpp - https://www.beyond-circuits.com/wordpress/vpp-pl-man-page *
• gcc - https://logological.org/gpp
• xpp - http://www.cross-browser.com/x/docs/xpp_reference.php
• vbpp - https://github.com/balanx/vbpp
• perlpp - https://github.com/MegabytePhreak/rdl/tree/master/perlpp
• ep3 - http://search.cpan.org/~mykl/Text-EP3-1.10/lib/Text/EP3.pm
• preprocess - https://pypi.python.org/pypi/preprocess/1.1.0

* - used by at least one ordt user