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Scott Nellenbach edited this page Jun 16, 2016 · 12 revisions

Welcome to the open-register-design-tool wiki!

a work in progress....

Toggle table of contents Pages 28

Home
Building Ordt from source
Cpp Model Outputs
Decoder and child region interface options
Hierarchical decoder example
JSpec Output
Options affecting RTL structure
Ordt Control Parameters
Other Outputs
Python Model Output
Running Ordt
Running Ordt Tests
Source contributions
SystemRDL examples
SystemRDL Output
SystemVerilog IO descriptions
SystemVerilog Output
Using JSpec input
Using SystemRDL input
UVM Model Output
uvm_reg_block_rdl methods
uvm_reg_field_rdl methods
uvm_reg_field_rdl_counter methods
uvm_reg_field_rdl_interrupt methods
uvm_reg_rdl methods
uvm_vreg_rdl methods
Verilog Testbench Output
XML Output and Viewer Utility

Home
Running Ordt
Building Ordt from source
Running Ordt Tests
Source contributions

Ordt Inputs

Ordt Control Parameters
Using SystemRDL input
Using JSpec input

Ordt Outputs

SystemVerilog Output
UVM Model Output
SystemRDL Output
JSpec Output
C++ Model Outputs
Python Model Output
Verilog Testbench Output
XML Output and Viewer Utility
Other Outputs

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