[BUG] VCD File not appearing after using the logic analyzer

**Describe the bug**
If you use the logic analyzer, there is no vcd file after you stop the simulation

**To Reproduce**
Steps to reproduce the behavior:
1. Use a wokwi diagram containing a logic analyzer
2. Record some samples
3. Stop the simulation
4. Nothing

**Expected behavior**
A .vcd file in the projet directory ?
