rtos: add handling for banked PSP registers (pyocd#1841)

RobertRostohar · web-flow · commit cc1ae68d4b15 · 2025-10-24T08:13:00.000+02:00
diff --git a/pyocd/rtos/argon.py b/pyocd/rtos/argon.py
@@ -1,5 +1,5 @@
 # pyOCD debugger
-# Copyright (c) 2016-2020 Arm Limited
+# Copyright (c) 2016-2020,2025 Arm Limited
 # SPDX-License-Identifier: Apache-2.0
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -197,8 +197,10 @@ def read_core_registers_raw(self, reg_list):
                 swStacked = 0x60
 
         for reg in reg_list:
-            # Must handle stack pointer specially.
-            if reg == 13:
+
+            # Must handle stack pointer(s) specially.
+            if (reg == index_for_reg('sp') or
+                reg == index_for_reg('psp')):
                 if inException:
                     reg_vals.append(sp + hwStacked)
                 else:
@@ -537,4 +539,3 @@ def name(self):
     @property
     def description(self):
         return "Argon RTOS"
-
diff --git a/pyocd/rtos/common.py b/pyocd/rtos/common.py
@@ -26,6 +26,11 @@
 # on the frame. The bit is 0 if the frame is extended.
 EXC_RETURN_EXT_FRAME_MASK = (1 << 4)
 
+## Mask on EXC_RETURN indicating whether a Secure or Non-secure stack is used
+# to restore stack frame on exception return. The bit is 0 if the Non-secure
+# stack is used or 1 if the Secure stack is used.
+EXC_RETURN_SECURE_STACK_MASK = (1 << 6)
+
 def read_c_string(context, ptr):
     """@brief Reads a null-terminated C string from the target."""
     if ptr == 0:
diff --git a/pyocd/rtos/freertos.py b/pyocd/rtos/freertos.py
@@ -1,5 +1,5 @@
 # pyOCD debugger
-# Copyright (c) 2016-2020 Arm Limited
+# Copyright (c) 2016-2020,2025 Arm Limited
 # SPDX-License-Identifier: Apache-2.0
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -15,7 +15,7 @@
 # limitations under the License.
 
 from .provider import (TargetThread, ThreadProvider)
-from .common import (read_c_string, HandlerModeThread, EXC_RETURN_EXT_FRAME_MASK)
+from .common import (read_c_string, HandlerModeThread, EXC_RETURN_EXT_FRAME_MASK, EXC_RETURN_SECURE_STACK_MASK)
 from ..core import exceptions
 from ..core.target import Target
 from ..core.plugin import Plugin
@@ -157,6 +157,7 @@ def __init__(self, parent, thread):
         super(FreeRTOSThreadContext, self).__init__(parent)
         self._thread = thread
         self._has_fpu = self.core.has_fpu
+        self._has_security_extension = Target.SecurityState.SECURE in self.core.supported_security_states
 
     def read_core_registers_raw(self, reg_list):
         reg_list = [index_for_reg(reg) for reg in reg_list]
@@ -179,11 +180,10 @@ def read_core_registers_raw(self, reg_list):
         else:
             sp = self._thread.get_stack_pointer()
 
-        # Determine which register offset table to use and the offsets past the saved state.
-        hwStacked = 0x20
-        swStacked = 0x20
-        table = self.NOFPU_REGISTER_OFFSETS
-        if self._has_fpu:
+        # Read exception LR (holds EXC_RETURN) to determine stacking info.
+        hasExtendedFrame = False
+        hasSecureStack = False
+        if self._has_fpu or self._has_security_extension:
             try:
                 if inException and self.core.is_vector_catch():
                     # Vector catch has just occurred, take live LR
@@ -193,20 +193,39 @@ def read_core_registers_raw(self, reg_list):
                     offset = self.FPU_BASIC_REGISTER_OFFSETS[-1]
                     exceptionLR = self._parent.read32(sp + offset)
 
-                # Check bit 4 of the saved exception LR to determine if FPU registers were stacked.
-                if (exceptionLR & EXC_RETURN_EXT_FRAME_MASK) != 0:
-                    table = self.FPU_BASIC_REGISTER_OFFSETS
-                    swStacked = 0x24
-                else:
-                    table = self.FPU_EXTENDED_REGISTER_OFFSETS
-                    hwStacked = 0x68
-                    swStacked = 0x64
+                # Check bit 4 of the exception LR to determine if FPU registers were stacked.
+                if (exceptionLR & EXC_RETURN_EXT_FRAME_MASK) == 0:
+                    hasExtendedFrame = True
+
+                # Check bit 6 of the exception LR to determine if Secure stack is used.
+                if (exceptionLR & EXC_RETURN_SECURE_STACK_MASK) != 0:
+                    hasSecureStack = True
+
             except exceptions.TransferError:
                 LOG.debug("Transfer error while reading thread's saved LR")
 
+        # Determine which register offset table to use and the offsets past the saved state.
+        if self._has_fpu:
+            if hasExtendedFrame:
+                table = self.FPU_EXTENDED_REGISTER_OFFSETS
+                hwStacked = 0x68
+                swStacked = 0x64
+            else:
+                table = self.FPU_BASIC_REGISTER_OFFSETS
+                hwStacked = 0x20
+                swStacked = 0x24
+        else:
+            table = self.NOFPU_REGISTER_OFFSETS
+            hwStacked = 0x20
+            swStacked = 0x20
+
         for reg in reg_list:
-            # Must handle stack pointer specially.
-            if reg == 13:
+
+            # Must handle stack pointer(s) specially.
+            if (reg == index_for_reg('sp') or
+                reg == index_for_reg('psp') or
+                (reg == index_for_reg('psp_s') and hasSecureStack) or
+                (reg == index_for_reg('psp_ns') and not hasSecureStack)):
                 if inException:
                     reg_vals.append(sp + hwStacked)
                 else:
diff --git a/pyocd/rtos/rtx5.py b/pyocd/rtos/rtx5.py
@@ -14,7 +14,7 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 from .provider import (TargetThread, ThreadProvider)
-from .common import (read_c_string, HandlerModeThread, EXC_RETURN_EXT_FRAME_MASK)
+from .common import (read_c_string, HandlerModeThread, EXC_RETURN_EXT_FRAME_MASK, EXC_RETURN_SECURE_STACK_MASK)
 from ..core import exceptions
 from ..core.target import Target
 from ..core.plugin import Plugin
@@ -135,6 +135,7 @@ def __init__(self, parent, thread):
         super(RTXThreadContext, self).__init__(parent)
         self._thread = thread
         self._has_fpu = self.core.has_fpu
+        self._has_security_extension = Target.SecurityState.SECURE in self.core.supported_security_states
 
     def read_core_registers_raw(self, reg_list):
         reg_list = [index_for_reg(reg) for reg in reg_list]
@@ -157,11 +158,10 @@ def read_core_registers_raw(self, reg_list):
         else:
             sp = self._thread.get_stack_pointer()
 
-        # Determine which register offset table to use and the offsets past the saved state.
-        hwStacked = 0x20
-        swStacked = 0x20
-        table = self.NOFPU_REGISTER_OFFSETS
-        if self._has_fpu:
+        # Read exception LR (holds EXC_RETURN) to determine stacking info.
+        hasExtendedFrame = False
+        hasSecureStack = False
+        if self._has_fpu or self._has_security_extension:
             try:
                 if inException and self.core.is_vector_catch():
                     # Vector catch has just occurred, take live LR
@@ -174,16 +174,32 @@ def read_core_registers_raw(self, reg_list):
 
                 # Check bit 4 of the exception LR to determine if FPU registers were stacked.
                 if (exceptionLR & EXC_RETURN_EXT_FRAME_MASK) == 0:
-                    table = self.FPU_REGISTER_OFFSETS
-                    hwStacked = 0x68
-                    swStacked = 0x60
+                    hasExtendedFrame = True
+
+                # Check bit 6 of the exception LR to determine if Secure stack is used.
+                if (exceptionLR & EXC_RETURN_SECURE_STACK_MASK) != 0:
+                    hasSecureStack = True
+
             except exceptions.TransferError:
                 LOG.debug("Transfer error while reading thread's saved LR")
 
+        # Determine which register offset table to use and the offsets past the saved state.
+        if hasExtendedFrame:
+            table = self.FPU_REGISTER_OFFSETS
+            hwStacked = 0x68
+            swStacked = 0x60
+        else:
+            table = self.NOFPU_REGISTER_OFFSETS
+            hwStacked = 0x20
+            swStacked = 0x20
+
         for reg in reg_list:
 
-            # Must handle stack pointer specially.
-            if reg == 13:
+            # Must handle stack pointer(s) specially.
+            if (reg == index_for_reg('sp') or
+                reg == index_for_reg('psp') or
+                (reg == index_for_reg('psp_s') and hasSecureStack) or
+                (reg == index_for_reg('psp_ns') and not hasSecureStack)):
                 if inException:
                     reg_vals.append(sp + hwStacked)
                 else:
@@ -244,7 +260,6 @@ def __init__(self, targetContext, provider, base):
         self._state = 0
         self._priority = 0
         self._thread_context = RTXThreadContext(self._target_context, self)
-        self._has_fpu = self._thread_context.core.has_fpu
         try:
             name_ptr = self._target_context.read32(self._base + RTXTargetThread.NAME_OFFSET)
             self._name = read_c_string(self._target_context, name_ptr)
diff --git a/pyocd/rtos/threadx.py b/pyocd/rtos/threadx.py
@@ -1,4 +1,5 @@
 # pyOCD debugger
+# Copyright (c) 2025 Arm Limited
 # Copyright (c) 2020-2021 Federico Zuccardi Merli
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -16,7 +17,8 @@
 
 from .provider import (TargetThread, ThreadProvider)
 from .common import (read_c_string, HandlerModeThread,
-                     EXC_RETURN_EXT_FRAME_MASK)
+                     EXC_RETURN_EXT_FRAME_MASK,
+                     EXC_RETURN_SECURE_STACK_MASK)
 from ..core import exceptions
 from ..core.target import Target
 from ..core.plugin import Plugin
@@ -175,6 +177,7 @@ def __init__(self, parent, thread):
         super(ThreadXThreadContext, self).__init__(parent)
         self._thread = thread
         self._has_fpu = self.core.has_fpu
+        self._has_security_extension = Target.SecurityState.SECURE in self.core.supported_security_states
         if self.core.architecture != CoreArchitecture.ARMv6M:
             # Use the default offsets for this istance
             self._nofpu_register_offsets = self.NOFPU_REGISTER_OFFSETS
@@ -205,11 +208,10 @@ def read_core_registers_raw(self, reg_list):
         else:
             sp = self._thread.get_stack_pointer()
 
-        # Determine which register offset table to use and the offsets past the saved state.
-        hwStacked = 0x20
-        swStacked = 0x24
-        table = self._nofpu_register_offsets
-        if self._has_fpu:
+        # Read exception LR (holds EXC_RETURN) to determine stacking info.
+        hasExtendedFrame = False
+        hasSecureStack = False
+        if self._has_fpu or self._has_security_extension:
             try:
                 if inException and self.core.is_vector_catch():
                     # Vector catch has just occurred, take live LR
@@ -221,16 +223,32 @@ def read_core_registers_raw(self, reg_list):
 
                 # Check bit 4 of the exception LR to determine if FPU registers were stacked.
                 if (exceptionLR & EXC_RETURN_EXT_FRAME_MASK) == 0:
-                    table = self.FPU_REGISTER_OFFSETS
-                    hwStacked = 0x68
-                    swStacked = 0x64
+                    hasExtendedFrame = True
+
+                # Check bit 6 of the exception LR to determine if Secure stack is used.
+                if (exceptionLR & EXC_RETURN_SECURE_STACK_MASK) != 0:
+                    hasSecureStack = True
+
             except exceptions.TransferError:
                 LOG.debug("Transfer error while reading thread's saved LR")
 
+        # Determine which register offset table to use and the offsets past the saved state.
+        if hasExtendedFrame:
+            table = self.FPU_REGISTER_OFFSETS
+            hwStacked = 0x68
+            swStacked = 0x64
+        else:
+            table = self._nofpu_register_offsets
+            hwStacked = 0x20
+            swStacked = 0x24
+
         for reg in reg_list:
 
-            # Must handle stack pointer specially.
-            if reg == 13:
+            # Must handle stack pointer(s) specially.
+            if (reg == index_for_reg('sp') or
+                reg == index_for_reg('psp') or
+                (reg == index_for_reg('psp_s') and hasSecureStack) or
+                (reg == index_for_reg('psp_ns') and not hasSecureStack)):
                 if inException:
                     reg_vals.append(sp + hwStacked)
                 else:
diff --git a/pyocd/rtos/zephyr.py b/pyocd/rtos/zephyr.py
@@ -1,5 +1,5 @@
 # pyOCD debugger
-# Copyright (c) 2016-2020 Arm Limited
+# Copyright (c) 2016-2020,2025 Arm Limited
 # Copyright (c) 2022 Intel Corporation
 # Copyright (c) 2022 Chris Reed
 # SPDX-License-Identifier: Apache-2.0
@@ -106,7 +106,8 @@ def read_core_registers_raw(self, reg_list):
         for reg in reg_list:
 
             # If this is a stack pointer register, add an offset to account for the exception stack frame
-            if reg == 13:
+            if (reg == index_for_reg('sp') or
+                reg == index_for_reg('psp')):
                 val = sp + exceptionFrame
                 LOG.debug("Reading register %d = 0x%x", reg, val)
                 reg_vals.append(val)
