Merge pull request #904 from mbrossard/feature/lpc4322_hic

SWO support for LPC4322 and other enhancements (non-exhaustive list):
- Update CMSIS DFP files
- Increase core clock to 120 MHz
- Improved GCC linker scripts

Author: mathias-arm

docs/hic/README.md

@@ -7,7 +7,7 @@
 | [kl26z](kl26z.md)             |  M0+ |  48 Mhz |  16 KB | 128 KB |  FS |
 | [kl27z](kl27z.md)             |  M0+ |  48 Mhz |  32 KB | 128 KB |  FS |
 | [lpc11u35](lpc11u35.md)       |  M0  |  48 Mhz |  12 KB |  64 KB |  FS |
-| [lpc4322](lpc4322.md)         |  M4  |  96 MHz | 256 KB | 256 KB |  HS |
+| [lpc4322](lpc4322.md)         |  M4  | 120 MHz | 256 KB | 256 KB |  HS |
 | [lpc55xx](lpc55xx.md)         |  M33 | 150 MHz | 272 KB | 320 KB |  HS |
 | [max32625](max32625.md)       |  M4  |  96 MHz | 160 KB | 512 KB |  FS |
 | [nrf52820](nrf52820.md)       |  M4  |  64 MHz |  32 KB | 256 KB |  FS |

docs/hic/lpc4322.md

@@ -1,7 +1,7 @@
 # lpc4322 HIC
 
 Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-sheet/LPC435X_3X_2X_1X.pdf)):
-- Cortex-M4 204 Mhz
+- Cortex-M4 204 Mhz (currently run at 120 MHz)
 - 512 KB Flash
 - 104 KB RAM
 - High-speed USB 2.0 device controller
@@ -16,7 +16,7 @@ Based on LPC4322JET100E chip ([Data Sheet](https://www.nxp.com/docs/en/data-shee
 
 Bootloader size is 64 KB
 
-## DAPLink default pin assignment 
+## DAPLink default pin assignment
 
 | Signal      | I/O | Symbol  | Pin |
 |-------------|:---:|---------|:---:|

records/board/lpc55S69xpresso.yaml

@@ -1,4 +1,6 @@
 common:
+    macros:
+            - SWO_UART=1
     sources:
         board:
             - source/board/lpc55S69xpresso.c

records/hic_hal/lpc4322.yaml

@@ -8,12 +8,14 @@ common:
         - CORE_M4
         - INTERNAL_FLASH
         - DAPLINK_HIC_ID=0x97969905  # DAPLINK_HIC_ID_LPC4322
-        - OS_CLOCK=96000000
+        - OS_CLOCK=120000000
     includes:
         - source/hic_hal/nxp/lpc4322
+        - source/hic_hal/nxp/lpc4322/RTE_Driver
     sources:
         hic_hal:
             - source/hic_hal/nxp/lpc4322
+            - source/hic_hal/nxp/lpc4322/RTE_Driver
 
 tool_specific:
     uvision:
@@ -32,6 +34,8 @@ tool_specific:
             hic_hal:
                 - source/hic_hal/nxp/lpc4322/armcc
     gcc_arm:
+        linker_file:
+            - source/hic_hal/nxp/lpc4322/gcc/lpc4322.ld
         sources:
             hic_hal:
                 - source/hic_hal/nxp/lpc4322/gcc

source/hic_hal/nxp/lpc4322/DAP_config.h

@@ -97,14 +97,16 @@ typedef unsigned int    BOOL;
 /// This configuration settings is used to optimize the communication performance with the
 /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
 /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
-#define DAP_PACKET_COUNT      1              ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
+#define DAP_PACKET_COUNT        8               ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
 
 /// Indicate that UART Serial Wire Output (SWO) trace is available.
 /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
+#if !defined(SWO_UART)
 #define SWO_UART                0               ///< SWO UART:  1 = available, 0 = not available
+#endif
 
 /// USART Driver instance number for the UART SWO.
-#define SWO_UART_DRIVER         0               ///< USART Driver instance number (Driver_USART#).
+#define SWO_UART_DRIVER         1               ///< USART Driver instance number (Driver_USART#).
 
 /// Maximum SWO UART Baudrate
 #define SWO_UART_MAX_BAUDRATE   10000000U       ///< SWO UART Maximum Baudrate in Hz
@@ -156,8 +158,6 @@ typedef unsigned int    BOOL;
 // State of Reset Ouput Enable buffer
 extern bool gpio_reset_pin_is_input;
 
-
-
 //**************************************************************************************************
 /**
 \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
@@ -440,6 +440,11 @@ It is recommended to provide the following LEDs for status indication:
 */
 __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit)
 {
+    if (bit) {
+        X_SET(LED_CONNECTED);
+    } else {
+        X_CLR(LED_CONNECTED);
+    }
 }
 
 /** Debug Unit: Set status Target Running LED.

source/hic_hal/nxp/lpc4322/IO_Config.h

@@ -42,6 +42,11 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC4322);
 #define PIN_SWDIO_IN_BIT      9
 #define PIN_SWDIO             (1<<PIN_SWDIO_IN_BIT)
 
+// SWO Pin                    P1_14:  GPIO1[7]
+#define PORT_SWO              1
+#define PIN_SWO_IN_BIT        7
+#define PIN_SWO               (1<<PIN_SWO_IN_BIT)
+
 // SWDIO Output Enable Pin    P1_5:  GPIO1[8]
 #define PORT_SWDIO_TXE        1
 #define PIN_SWDIO_TXE_IN_BIT  8
@@ -57,15 +62,27 @@ COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_LPC4322);
 #define PIN_RESET_TXE_IN_BIT  6
 #define PIN_RESET_TXE         (1<<PIN_RESET_TXE_IN_BIT)
 
-// ISP Control Pin          P2_11:  GPIO1[11]
-#define ISPCTRL_PORT        1
-#define ISPCTRL_BIT         11
+// ISP Control Pin            P2_11:  GPIO1[11]
+#define PORT_ISPCTRL          1
+#define PIN_ISPCTRL_IN_BIT    11
+#define PIN_ISPCTRL           (1<<PIN_ISPCTRL_IN_BIT)
+
+// Connected LED              P1_1: GPIO0[8]
+#define PORT_LED_CONNECTED    0
+#define PIN_LED_CONNECTED_IN_BIT   8
+#define PIN_LED_CONNECTED     (1<<PIN_LED_CONNECTED_IN_BIT)
+
+// Power Enable               P3_1: GPIO5[8]
+#define PORT_POWER_EN         5
+#define PIN_POWER_EN_BIT      8
+#define PIN_POWER_EN          (1<<PIN_POWER_EN_BIT)
 
 #define X_SET(str)     LPC_GPIO_PORT->SET[PORT_##str] = PIN_##str
 #define X_CLR(str)     LPC_GPIO_PORT->CLR[PORT_##str] = PIN_##str
 #define X_DIR_OUT(str) LPC_GPIO_PORT->DIR[PORT_##str] |= (PIN_##str)
 #define X_DIR_IN(str)  LPC_GPIO_PORT->DIR[PORT_##str] &= ~(PIN_##str)
 #define X_BYTE(str)    LPC_GPIO_PORT->B[(PORT_##str << 5) + PIN_##str##_IN_BIT]
+#define X_WORD(str)    LPC_GPIO_PORT->W[(PORT_##str << 5) + PIN_##str##_IN_BIT]
 
 
 #endif